ASIC Jobs in Massachusetts.
All active ASIC roles based in Massachusetts.
Pick a job to read the details
Tap any role on the left — its description and apply link will open here.
Analog Design Automation Intern
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
At Tenstorrent, die-to-die (D2D) interfaces are how we stitch chiplets together into scalable AI and RISC‑V systems, delivering the bandwidth, latency, and power efficiency our architecture demands. As these links push signaling, process, and packaging limits, we rely on robust analog design automation to explore architectures quickly, verify complex corners, and deliver reliable Silicon at scale.
In this role, you will help build and refine automation that our analog designers use every day to design, simulate, and validate D2D PHYs. Your work on flows, scripts, and analysis frameworks will directly impact how fast we can iterate on D2D interfaces, how confidently we can sign them off, and ultimately how Tenstorrent connects and scales its next-generation AI hardware.
This role is hybrid based out of Toronto, Boston, Austin or Santa Clara (preferred).
Who You Are
- A flexible thinker who is excited by the future of AI and eager to work at the boundary between analog circuits and advanced packaging.
- Strong proficiency in Python code conventions
- A curious and motivated student eager to connect the dots between Analog IC design, Data Analytics, and AI/ML tools.
- Interested in how architectural ideas become silicon products and how automation can accelerate the design cycle.
What We Need
- A co-op or PEY student pursuing a BS/MS/PhD in Electrical Engineering with academic exposure to Analog IC design.
- Interest in or academic exposure to Machine Learning concepts (e.g., data analysis, basic model training, optimization).
- Interest in applying Open Source packages and tools to analog design automation problems.
- Strong analytical thinking and communication skills.
What You’ll Learn
- Analog design challenges and solutions in modern FinFET processes.
- Deploy SW for HW Design Automation
- Collaborate with senior Analog and Design Automation engineers to gain insight into the full ASIC design methodology and how automation drives product success.
Compensation for all interns at Tenstorrent ranges from $35/hr - $70/hr including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Ready to apply?
Apply to Tenstorrent University Jobs
Sr Staff Engineer, ASIC Design Methodology
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We are looking for an ASIC Design Methodology Engineer to advance our design infrastructure and flows across RTL development, verification, and physical implementation. This role is ideal for engineers who thrive on improving design quality, enabling scalability, and automating methodologies that accelerate silicon success.
This role is hybrid, based out of Toronto, Ottawa, Austin, or Boston.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- A strong advocate for design quality and productivity, with expertise in ASIC design flows.
- Skilled in RTL design and familiar with static and dynamic analysis tools.
- Comfortable automating design checks and improving methodology for scalability and reuse.
- A collaborative engineer who partners effectively across RTL, verification, and backend teams.
What We Need
- Develop and maintain ASIC design methodologies and infrastructure for RTL development and integration.
- Own and evolve static code analysis (Lint, CDC, RDC, DFT) and RTL-netlist logic equivalency design methodologies
- Develop synthesis timing constraints (SDC) and low power design specifications (UPF)
- Support RTL-to-GDS flow enablement, ensuring clean handoffs and sign-off readiness.
- Collaborate with EDA vendors and internal tool owners to optimize performance, quality, and runtime.
What You Will Learn
- How large-scale AI SoCs are architected, integrated, and brought to silicon.
- How methodology choices directly impact design performance, power, and verification closure.
- How to build and scale ASIC design flows supporting cutting-edge compute architectures.
- How to integrate cross-functional workflows across design, DFT, DV, physical, and firmware teams.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Ready to apply?
Apply to Tenstorrent