We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance chiplet based SoC architectures. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance and power aware design.

This role is hybrid, based out of Tokyo.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A digital design expert with a deep understanding of computer architecture and IP microarchitecture.
• Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows.
• Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals.
• A naturally collaborative and technical engineer — you thrive in spec definition, peer reviews, and team-wide planning.
• Strong synthesis and timing closure awareness to support backend teams.

What We Need

• Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL.
• Architecture and RTL implementation of Tenstorrent’s custom IP blocks and SoC components.
• Performance-aware design decisions for compute, interconnect, or memory-heavy blocks.
• Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows.
• Prior experience in on-chip fabric and interconnect designs and basic understanding of RISC-V Architecture and debug experience is preferable.

What You Will Learn

• How cutting-edge chiplet design are built, from spec to silicon.
• What it takes to collaborate with teams designing novel processor and memory architectures.
• How cross-functional workflows come together across design, DV, physical, and firmware teams.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

The Role:

Radio Frequency (RF) Engineer at ASM will provide solutions for difficult RF technical issues associated with specific projects, contribute to the timely completion of specific programs and projects, possess the ability to work on complex assignments with some guidance and direction from the Engineering Manager.

Responsibilities:

• Develop RF module and reactor of ASM products.
• Using conventional RF source and antennas provide reliable structure to provide stable performance in extreme and harsh conditions.

• Troubleshooting and modification of RF generator and matching network
• Understanding plasma characterization and troubleshooting the Plasma/RF related issues

• Coding FPGA chips to control modules and parts to maximize plasma performance of ASM Products

Education & Experience:

• Master's or Ph. D Degree in Electronics, Physics, or relevant disciplines.
• 3+ year experience in RF plasma field which including modules and parts is preferred.
• Have a broad-based background in analysis, design and debug of complex RF systems.
• Design, implement, maintain, and improve electrical instruments, equipment, facilities, components, products, and systems for the semiconductor equipment industry.
• Well versed with the requirements of CE, NEC, IEC, NFPA, VDE, SEMI S2-95 and other relevant standards as applicable to semiconductor manufacturing equipment.
• Experience with modularizing semiconductor equipment designs for offline assembly.
• Experienced using Microsoft applications such as Excel, Word, PowerPoint, and Project; Manufacturing Requirements Planning (MRP); AutoCAD; OrCAD or Altium schematic capture.
• Business level English

Functional Knowledge

• Plasma Deposition product knowledge a plus (CVD, ALD, EPI, PECVD, PEALD)

Summary

QuEra Computing, Inc. seeks a creative and collaborative Scientific Software Engineer to help solve the unique software challenges of integrating high-level applications into state-of-the-art neutral-atom quantum computers. You will have the opportunity to work with a vibrant scientific software team and a community of industry and academic collaborators and to help our growing team of diverse experts address fascinating challenges, ranging from classical compiler techniques to direct integration with low-level hardware components. Using our open-source toolchain, Kirin, you will be building QuEra’s compiler pipeline together with experimental & computational physicists from low-level hardware instructions to high-level programming languages. This involves the development of new features and infrastructure for hardware execution. You will be co-designing compilers and hardware infrastructure for the next generation of quantum computing using cutting-edge neutral-atom and quantum error correction technologies. This new direction involves multiple new challenges in both engineering and science. 

This Japan-based role also includes maintenance and updates of the internal execution software pipeline for the Gemini class machine deployed at AIST (ABCIQ). The primary audience for these tools and workflows is internal researchers and experimentalists, and the work is closely connected to hardware/control electronics and lab execution needs. 

Responsibilities

• Develop and maintain domain-specific language (DSL) for pulse-level programs and its associated compilation stack 
• Support integration of pulse compilation into multiple quantum computer builds 
• Collaborate with Quantum Error Correction (QEC) scientists and hardware control team to plan and develop hardware features required for executing QEC algorithms 
• Collaborate with other members of the scientific software team to integrate gate-level and atom-move compilation 
• Maintain and update the internal execution software pipeline for the Gemini class machine deployed in AIST (ABCIQ), ensuring compatibility with evolving hardware/control capabilities and internal research workflows 

Qualifications

• Masters in Computer Science with focus on quantum computation/architecture/programming language/compiler, or equivalent professional experience 
• Enthusiastic about building tools used by non-software developers 
• Experience with Python semantics, Python type hints, CPython interpreter 
• Experience with modern C++ projects and tooling around those projects 
• Experience with Static Single Assignment intermediate representations-based compiler 
• Knowledge of the full lifecycle of software development, including version control, code review, testing, CI/CD, logging, profiling, debugging, and documentation 
• Business-level proficiency in Japanese and English (spoken and written) for technical collaboration with Japan-based stakeholders and QuEra’s global teams 

Preferred Qualifications

• Ph.D. in Computer Science with focus on quantum computation/architecture/programming language/compiler, or equivalent professional experience 
• Experience with FPGA programming 
• knowledge in quantum physics and AMO physics 
• Experience in programming language design, especially programming language theory 
• knowledge in quantum error correction 
• Contribution to existing open-source libraries 

科学ソフトウェアエンジニア - ハードウェアコンパイル（日本） 

職務内容 

QuEra Computing, Inc.では、最先端の中性原子量子コンピュータへの高レベルアプリケーションの統合という独自のソフトウェア課題の解決を支援する、創造性と協調性を兼ね備えた科学ソフトウェアエンジニアを募集しています。活気ある科学ソフトウェアチームや産学の協力者コミュニティと共に働き、古典的なコンパイラ技術から低レベルハードウェアコンポーネントとの直接統合に至るまで、多様な専門家からなる成長中のチームが取り組む魅力的な課題の解決に貢献する機会を得られます。当社のオープンソースツールチェーン「Kirin」を活用し、実験物理学者や計算物理学者と共に、低レベルのハードウェア命令から高レベルのプログラミング言語に至るまで、QuEraのコンパイラパイプラインを構築していただきます。これには、ハードウェア実行のための新機能やインフラの開発が含まれます。最先端の中性原子技術や量子エラー訂正技術を用いて、次世代量子コンピューティングのためのコンパイラおよびハードウェアインフラを共同設計していただきます。この新たな方向性には、工学と科学の両面で数多くの新たな課題が伴います。 

この日本拠点での役割には、産業技術総合研究所（AIST）に配備されたGeminiクラスのマシン（ABCI-Q）向けの内部実行ソフトウェアパイプラインの保守および更新も含まれます。これらのツールやワークフローの主な利用者は内部の研究者や実験担当者であり、業務はハードウェア／制御電子機器や実験室での実行要件と密接に関連しています。 

職務内容 

• パルスレベルプログラム用のドメイン特化言語（DSL）および関連するコンパイルスタックの開発・保守 

• 複数の量子コンピュータ構築へのパルスコンパイルの統合を支援 

• 量子エラー訂正（QEC）の科学者やハードウェア制御チームと協力し、QECアルゴリズムの実行に必要なハードウェア機能の計画・開発を行う 

• 科学ソフトウェアチームの他のメンバーと協力し、ゲートレベルおよび原子移動のコンパイルを統合する 

• 産業技術総合研究所（AIST）に配備されたGeminiクラスマシン（ABCI-Q）向けの内部実行ソフトウェアパイプラインを維持・更新し、進化するハードウェア／制御機能および内部の研究ワークフローとの互換性を確保する 

応募資格 

• 量子計算／アーキテクチャ／プログラミング言語／コンパイラを専門とするコンピュータサイエンスの修士号、または同等の実務経験 

• ソフトウェア開発者以外が使用するツールの構築に熱意があること 

• Pythonのセマンティクス、Pythonの型ヒント、CPythonインタプリタに関する経験 

• 最新のC++プロジェクトおよびそれらに関連するツールに関する経験 

• 静的単一代入（SSA）中間表現ベースのコンパイラに関する経験 

• バージョン管理、コードレビュー、テスト、CI/CD、ロギング、プロファイリング、デバッグ、ドキュメント作成を含む、ソフトウェア開発の全ライフサイクルに関する知識 

• 日本国内のステークホルダーおよびQuEraのグローバルチームとの技術的な連携を行うための、日本語および英語（会話・文章）におけるビジネスレベルの習熟度 

望ましい資格 

• 量子計算/アーキテクチャ/プログラミング言語/コンパイラを専門とするコンピュータサイエンスの博士号、または同等の実務経験 

• FPGA プログラミングの経験 

• 量子物理学および AMO 物理学の知識 

• プログラミング言語の設計、特にプログラミング言語理論の経験 

• 量子エラー訂正の知識 

• 既存のオープンソースライブラリへの貢献