About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?  

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

Summary

As a Senior Staff Hardware Engineer in Design Verification, you will own verification strategy and execution for complex SoC / IP blocks, driving quality from architecture through tape‑out. You will define methodology, lead test plan creation, guide junior engineers, and be a key technical partner to architecture, design, and validation teams.

Key Responsibilities

• Verification Ownership

  • Own verification for one or more complex subsystems (CPU/LSU/cache/interconnect/IP blocks).

  • Define verification strategy, methodology, and test plans from spec/architecture documents.

  • Ensure coverage closure (functional, code, assertion, and scenario coverage) to sign‑off criteria.

• Testbench Architecture & Implementation

  • Architect and implement constrained‑random, coverage‑driven testbenches (System Verilog/UVM or equivalent).

  • Develop reusable verification components: agents, monitors, scoreboards, checkers, and VIP integrations.

  • Drive block‑level and subsystem‑level test environments, including stimulus generation and self‑checking.

• Formal & Assertion‑based Verification

  • Specify and implement assertion sets (SVA or similar) for critical micro‑architectural properties.

  • Apply formal verification on key blocks (protocols, arbiter, FIFOs, control logic) to complement simulation.

• Debug & Quality

  • Lead bring‑up and debug of complex failures (functional, performance, corner‑case, and silicon escapes).

  • Work closely with RTL designers to root‑cause bugs and propose fixes or micro‑architectural clarifications.

  • Define and track verification metrics; report status, risks, and mitigation plans.

• Methodology & Infrastructure

  • Define and evolve DV methodology (UVM usage, regression strategy, coverage methodology, reuse across projects).

  • Collaborate with CAD/infra teams to improve regressions, farm utilization, CI pipelines, and debug flows.

  • Introduce and evaluate new tools/flows (formal, lint, CDC, low‑power, emulation/FPGA prototyping).

• Technical Leadership & Mentoring

  • Provide technical leadership to DV teams across projects; act as a subject‑matter expert for key IP/flows.

  • Mentor junior and mid‑level DV engineers in testbench design, debugging, methodology, and best practices.

  • Review and sign off on test plans, environments, and coverage for other team members.

• Cross‑functional Collaboration

  • Partner with architects and RTL designers to refine micro‑architecture for verifiability and testability.

  • Coordinate with software, validation, and post‑silicon teams to ensure end‑to‑end coverage of use‑cases.

  • Participate in spec reviews, micro‑architecture reviews, and tape‑out sign‑off reviews.

Required Qualifications

• Education / Experience

  • BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.

  • Typically 10+ years of experience in ASIC/SoC/IP design verification, with demonstrated senior/staff‑level impact.

• Technical Skills

  • Strong expertise in SystemVerilog and UVM (or comparable class‑based verification methodologies).

  • Proven experience verifying complex CPU/SoC/IP blocks (e.g., cache/memory subsystem, interconnect, accelerators, IO).

  • Solid understanding of digital design concepts: pipelines, coherency, memory hierarchy, clocking, resets, CDC.

  • Hands‑on experience with:

    • Functional and code coverage, coverage‑driven verification.

    • Assertion‑based verification (SVA).

    • Debug tools (e.g., Verdi, DVE, SimVision) and waveform‑based debug.

  • Experience with industry‑standard simulators (VCS, Xcelium, Questa, etc.) and regression infrastructure.

• Domain Knowledge

  • Good understanding of one or more: CPU microarchitecture (e.g. RISC‑V/ARM/x86), cache coherence, memory protocols, on‑chip interconnects, or high‑speed interfaces.

  • Familiarity with standard on‑chip/off‑chip protocols (e.g. AXI, TileLink).

• Soft Skills

  • Strong analytical and problem‑solving skills; able to drive issues from ambiguity to closure.

  • Excellent written and verbal communication; comfortable presenting technical topics and status to broader teams.

  • Demonstrated ability to lead technically across functions and to mentor other engineers.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.