Subsystem & Protocol Experts with Focus on Architecture, High-level Integration, Bus Fabric, connectivity PCIe/ UCIe, NoC, and High-Bandwidth Protocols.

SoC Subsystem Design Engineer - High-Speed Interconnect (PCIe/UCIe) OR Storage & Peripheral Fabric (UFS/MMC/USB) OR Low-Speed Peripheral Fabric

Focus: Global connectivity PCIe/ UCIe, NoC, and High-Bandwidth Protocols.

Qualifications:

1.      5 –18 years of experience in SoC/IP RTL Design and Subsystem Architecture.

2.      Strong expertise in storage or high-speed peripheral protocols, including UFS, MMC, and USB (2.0/3.0/SS), PCIe and UCIe, I2C, I3C, SMBus, SPI, UART Etc

3.      Sound knowledge of the complete AMBA protocol stack, specifically AXI, AHB, and APB.

4.      Expert-level experience in low-power architecture design using UPF and VCLP.

5.      Proven track record in managing GLS (Gate Level Simulation) closure and implementing Functional ECOs.Advanced expertise in high-speed serial protocols, specifically PCIe Gen 5/6/7 and UCIe specifications.

6.      Sound knowledge of the complete AMBA protocol stack, with mastery of CHI, ACE, and AXI.

7.      Proven experience in NoC (Network-on-Chip) concepts, interconnect topology, and performance/latency tuning.

8.      Deep understanding of SDC constraints, STA Timing analysis, and high-frequency timing closure.

9.      Strong grasp of RTL Lint, CDC, SDC constraints, and DFT checks for complex subsystems.

•              Job Summary: Lead the architectural definition and subsystem-level integration

•              Key Responsibilities:

1.      Architectural Definition: Define the subsystem structure and NoC concepts for PCIe Gen 5/6/7 and UCIe ,. Create micro-architecture and Hardware Design Documents (HDD).

2.      Protocol Mastery: Ensure strict compliance with AMBA CHI, ACE, and AXI protocols for high-performance data movement.

3.      System Integration: Manage the integration of interconnect IPs into the SoC top-level, focusing on latency tuning and bandwidth optimization.

4.      Quality & Timing: Drive SDC constraints, STA Timing analysis, and Formality checks at the subsystem level.

5.      Validation & Collab: Lead pre- and post-silicon validation and work collaboratively with global SoC teams across various geographies.

6.      Flows: Oversee RTL Lint, CDC, UPF/VCLP low-power checks, and DFT checks. Use Verdi for system-level debugging.

• Qualifications:

 5–18 years of experience in SoC/IP RTL Design and Subsystem Architecture.

Advanced expertise in high-speed serial protocols, specifically PCIe Gen 5/6/7 , UCIe , UFS, MMC,USB ,PCIe and UCIe, I2C, I3C, SMBus, SPI, UART Etc  specifications.

Sound knowledge of the complete AMBA protocol stack, with mastery of CHI, ACE, and AXI.

 Proven experience in NoC (Network-on-Chip) concepts, interconnect topology, and performance/latency tuning.

 Deep understanding of SDC constraints, STA Timing analysis, and high-frequency timing closure.

 Experience in driving system-level RTL Lint, CDC, Formality, and Low-power checks (UPF, VCLP).

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

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