Job Details:

Job Description:

Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are at the core of enabling customers to efficiently map complex designs to cutting-edge FPGA architectures.

This role focuses on developing and optimizing FPGA placement algorithms within the compiler toolchain, directly impacting performance, power efficiency, and overall design quality.

As part of the Quartus team, your responsibilities will include, but are not limited to: 

• Placement Algorithm Development:
  Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.

• Compiler Flow Enhancement:
  Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams.

• Performance Optimization:
  Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.

• Timing-Driven Placement:
  Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs.

• Debug & Analysis:
  Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.

• Toolchain Integration:
  Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.

Qualifications:

• Bachelor's Degree in CS, Computer Engineering, or related field

• Working experience with C++

• Experience with Verilog, Python and TCL is a plus

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