Sobre este puesto de Engineering Program Manager, RISCV en Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We're looking for an Engineering Program Manager — or a technical engineer ready to move into program management — to help drive execution on our RISC-V CPU team. You'll work across architecture, design, verification, physical design, and DFT to keep a high-performance CPU program moving from spec through tapeout and post-silicon debug. Partnering with a senior program lead and engineering managers, you'll own schedules, track milestones, surface risks early, and keep cross-functional teams aligned.
This role is hybrid, based out of Austin, TX or Santa Clara, CA.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- Experience in CPU, SoC, or silicon development — as an engineer, technical lead, or program manager.
- Comfortable working with cross-functional engineering teams and translating technical detail into clear status, dependencies, and trade-offs.
- Organized and proactive; you chase down open items rather than waiting for them to resolve.
- A clear communicator who can hold your own in engineering discussions and write updates leadership can act on.
What We Need
- Support the full CPU development cycle — spec, design, verification, DFT, tapeout, and post-silicon debug — owning defined workstreams end to end.
- Build and maintain schedules, track dependencies and resourcing, and drive execution across engineering teams.
- Hands-on experience with at least one silicon program through a major milestone (tapeout, bring-up, or IP release).
- Identify and escalate risks, and help drive them to closure.
- Exposure to Functional Safety (FuSa) standards, especially ISO 26262, and automotive hardware development requirements is a plus.
What You Will Learn
- How cutting-edge RISC-V CPU IP is delivered at scale, both internally and for external customers.
- How to work alongside senior engineers on real-time design challenges and schedule trade-offs.
- How to run project reviews and report metrics, risks, and mitigation plans to senior leadership.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
