𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟮𝟬𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟱𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟮𝟬-𝟱𝟬 𝗟𝗣𝗔)

Experience: 8+ yrs

Location: Hyderabad, Telangana, India

As a Physical Design Engineer, you will drive the creation of high-performance, low-power silicon solutions by translating complex RTL designs into manufacturable, taped-out chips. Leveraging your deep expertise in VLSI layout, you will optimize placement, clock tree synthesis, and routing while ensuring adherence to timing, power, and area constraints. Your role will involve close collaboration with synthesis, verification, and test teams to deliver designs that meet stringent performance and yield targets. You will also mentor junior engineers and contribute to process improvements that enhance productivity and design quality across the development lifecycle.

Requirements

𝗞𝗲𝘆 𝗥𝗲𝘀𝗽𝗼𝗻𝘀𝗶𝗯𝗶𝗹𝗶𝘁𝗶𝗲𝘀

• Lead the physical design flow from floorplanning to tape-out for ASIC and SoC projects.

• Perform rigorous static timing analysis and resolve timing violations using industry tools such as Synopsys IC Compiler and PrimeTime.

• Optimize power consumption through leakage and dynamic power analysis and implement voltage scaling techniques.

• Interface with floorplanning and clock tree synthesis teams to balance area, timing, and power trade‑offs.

• Conduct detailed layout verification using DRC, LVS, and parasitic extraction tools.

• Generate and maintain comprehensive design documentation, including mask data and physical design specifications.

• Coordinate with tape‑out facilities to ensure correct fabrication data transfer and layout compliance.

• Analyze and debug manufacturing issues post‑tape‑out to identify process or design root causes.

• Participate in design reviews and provide constructive feedback to improve design quality.

• Stay updated on the latest VLSI physical design methodologies, tools, and industry best practices.

𝗪𝗵𝗮𝘁 𝗠𝗮𝗸𝗲𝘀 𝗬𝗼𝘂 𝗮 𝗚𝗿𝗲𝗮𝘁 𝗙𝗶𝘁

• 8+ years of proven experience in physical design for complex ASIC or SoC projects.

• Strong command of VLSI layout tools, particularly Synopsys IC Compiler, Mentor Calibre, and Cadence Innovus.

• Deep knowledge of static timing analysis techniques using Synopsys PrimeTime or equivalent.

• Proficiency in power analysis and optimization, including implementation of power‑gating and clock‑domain crossing strategies.

• Demonstrated experience with DRC/LVS verification and parasitic extraction workflows.

• Excellent problem‑solving skills with a track record of resolving critical timing and layout issues under tight deadlines.

• Strong communication and teamwork abilities, capable of collaborating across multi-disciplinary engineering teams.

• Familiarity with EUV and 14nm/7nm process design kits and related manufacturing constraints.

• Ability to mentor junior engineers and contribute to process enhancement initiatives.

• Holds a Bachelor’s or Master’s degree in Electrical Engineering, VLSI Design, or a related field.