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Job Description:

Develops the logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Creates prototypes, simulates models, and specifies systems requirements. Prepares and designs logic diagrams and codes for implementing system design and test specifications. Delivers software models for device level bring up, including user visible functionality, timing, and power. Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

Qualifications:

- Bachelor's degree in Electrical, Electronics, Computer Engineering or equivalent. 

- Experienced in FPGA, custom IC or ASIC design and demonstrated excellence in any of the product development areas, from architecture, design, validation, to product. 

- 8+ years of experience in RTL design with Verilog and VHDL.

- Familiar with logic simulations and design verification.

- Knowledge of Ethernet/ ANLT and NIOS is desired.

- Familiarity with Python, Perl, TCL and shell scripts is a plus. 

- Highly motivated to learn and adapt to fast-changing technologies and environments. 

- Exceptional analytical, problem-solving and communication skills; initiative, promote innovation and teamwork. 

- Self-motivated and able to excel in a team environment. 

- Demonstrates fundamental values such as accountability, integrity and a winning mindset.

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