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Job Description:

We are seeking a Senior FPGA Soft IP Development Engineer to own the architecture, micro-architecture, and parameterizable RTL design of high-performance soft intellectual property (IP) blocks. In this role, you will be responsible for developing critical system-level IP cores—including advanced AMBA AXI Interconnect IP - ensuring their portability, scalability, and timing closure across diverse FPGA architectures.

Responsibilities

• Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic, and system interfaces
• Collaborate closely with the verification team to shape test plans and improve verification coverage
• Work with the physical design team to understand and resolve timing, power, and congestion challenges
• Work with the verification team on regression failure debug and root cause, and provide RTL fixes if necessary
• Provide technical support to the FAE team on pre-sales customer engagements
• Provide technical support to the AE team on post-sales customer deliveries
• Apply working knowledge of CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis within the design flow
• Develop RTL micro-architecture from scratch
• Provide technical guidance and mentorship to other engineers while remaining a hands-on individual contributor

Required Qualifications & Technical Skills

• Education & Experience: bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5+ years of dedicated RTL/FPGA design experience.
• Protocol Expertise: Deep, hands-on knowledge of the AMBA AXI4 protocol suite and high-speed memory interfaces.
• Toolchains: Proficiency with FPGA implementation tools and EDA simulation software (Siemens Questa/Modelsim, Synopsys VCS).
• Scripting: Strong scripting skills in Python, Tcl, or Perl for build automation and test automation.

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