𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟴𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟭𝟮𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟴-𝟭𝟮 𝗟𝗣𝗔)

Experience: 1+ yrs

Location: Hyderabad

We are looking for a detail-oriented and technically skilled Data Verification Engineer with hands-on knowledge of Verilog and Gate-Level Simulation (GLS) to support digital design verification and validation activities. The ideal candidate will have a strong foundation in digital logic, RTL design concepts, simulation methodologies, and hardware verification workflows.

This role is suited for an engineer who is passionate about semiconductor design, functional correctness, and identifying potential issues before hardware implementation. You will work with design and verification teams to validate digital circuits, analyse simulation results, investigate mismatches, and ensure design reliability throughout the development lifecycle.

Requirements

Key Responsibilities

• Develop, execute, and maintain verification test scenarios for digital hardware designs using Verilog-based environments.
• Support Gate-Level Simulation (GLS) activities using synthesised netlists and appropriate simulation models.
• Analyse RTL and gate-level simulation results to verify design functionality and identify discrepancies.
• Review design specifications and translate functional requirements into verification scenarios.
• Debug simulation failures by analysing waveforms, signal transitions, timing behaviour, and log files.
• Investigate mismatches between RTL and gate-level simulation results and coordinate with design teams to identify root causes.
• Support simulations with timing annotation, including Standard Delay Format (SDF), where applicable.
• Identify potential timing-related issues, including setup and hold violations, glitches, and unknown signal values.
• Work with verification engineers to improve test coverage, testbench quality, and simulation reliability.
• Execute regression tests and maintain accurate records of test results, failures, and verification status.
• Assist in debugging issues related to reset sequences, clock behaviour, signal connectivity, and logic functionality.
• Collaborate with RTL Design, Physical Design, and Verification teams to resolve design and simulation issues.
• Maintain technical documentation, verification reports, and debugging notes.
• Follow established verification methodologies, coding standards, and project quality processes.

What Makes You a Great Fit

• 1+ year of experience in digital design verification, semiconductor engineering, or a related hardware design role.
• Strong foundational knowledge of Verilog HDL and digital logic design.
• Familiarity with Gate-Level Simulation (GLS) and the simulation of synthesised netlists.
• Understanding of RTL design, combinational and sequential logic, clocks, resets, and timing concepts.
• Familiarity with simulation tools such as Cadence Xcelium, Synopsys VCS, or Siemens Questa is an advantage.
• Basic understanding of SDF annotation, timing checks, and simulation mismatches.
• Ability to analyse simulation logs and waveforms using waveform viewers and debugging tools.
• Familiarity with Linux environments, command-line tools, and basic scripting is beneficial.
• Strong analytical, debugging, and problem-solving skills with attention to detail.
• Good communication skills and the ability to collaborate effectively with cross-functional engineering teams.
• A bachelor's or master's degree in Electronics Engineering, Electrical Engineering, VLSI, Computer Engineering, or a related discipline is preferred.