Tenstorrent is seeking a Layout Engineer with expertise in board layout for high-performance computing and  AI hardware. This role requires direct experience with multi-layer boards, HDI vias, blind vias, back drilling, DFM, DFA and routing / layout of interfaces like GDDR, LPDDR, DDR, PCIe Gen 5 & 6, Ethernet IEEE 802.3bj, cd, cf, USB, etc. The ideal candidate will work closely with cross-functional teams consisting of engineers from systems, power, signal integrity and mechanical to ensure that our products meet the layout margins and cutting-edge specifications for mass production boards for data centers, workstations, and consumer computing applications.

This role is hybrid, based out of Toronto, ON or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• Experienced board layout engineer with ~8+ years in PCB design (Cadence Allegro; Altium a plus).
• Hold a B.S. in EE, CS, or equivalent experience.
• Strong background in high-speed, complex PCBs (high layer count, HDI, multi-lamination, VIPPO, back drilling).
• Comfortable defining and applying layout rules (physical, spacing, length-matching) for high-speed designs.
• Confident working with fabricators on stackups, capabilities, and resolving DFM/DFA/DFT feedback.
• Detail-oriented owner of designs with strong communication skills and the ability to work with an international, cross-functional team.

What we need

• A Layout Engineer to own multi-layer PCB layouts for high-performance computing and AI hardware.
• Expertise routing GDDR, LPDDR, DDR, PCIe Gen 5/6, Ethernet (IEEE 802.3bj/cd/cf), USB and other high-speed interfaces.
• Proficiency with Cadence schematic/layout tools (v25.1) in the Cadence Pulse environment.
• Ability to choose appropriate advanced fabrication technologies (HDI, blind/buried vias, VIPPO, back drilling) balancing performance and cost.
• Skill in floorplanning, component placement, board connectivity, and creation of power/ground planes.
• Collaboration with power, signal integrity, and mechanical engineers to meet PDN, SI, mechanical, thermal, and regulatory (IPC, UL, CE, RoHS, FCC) requirements.

What you will learn

• How to design boards for cutting-edge AI and high-performance computing systems in data center, workstation, and consumer products.
• Techniques to optimize signal integrity, power delivery, and manufacturability for mass-production hardware.
• Best practices for working in a deeply cross-functional environment across systems, power, SI, and mechanical teams.
• Practical experience building around a from-scratch, high-performance RISC-V CPU and AI-first compute platform.
• How to navigate and integrate global industry and regulatory standards while pushing performance limits.
• The direct impact of your layout work on the roadmap and success of a fast-growing AI silicon and systems company.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking a Signal Integrity Engineer to join our growing team. The ideal candidate will have a wealth of exposure designing high speed interconnects, breakout design, material trade-offs and verification. A background in electrical engineering, electronics or relevant fields is required. Must love all things high speed!

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Toronto, ON.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a Bachelor’s degree in Electrical Engineering (or equivalent) and 5+ years working in high-speed digital design with a focus in high-speed PCB or package design at 10Gbps and above (e.g. 100GbE, GDDR6, PCIe Gen5+).
• You’re comfortable working with high-speed performance metrics such as ICR, ERL, COM, NEXT, and FEXT as well as knowledge of high-speed connector technologies, including NPO, CPO, and emerging standards.
• You are proficient with PCB ECAD tools (ideally Cadence Allegro).
• You communicate clearly (written and verbal), think critically, and love solving complex signal integrity problems.
• You’re enthusiastic about all things high speed and enjoy collaborating across teams

What We Need

• Design, extract, and simulate complex breakout structures, including end-to-end simulations and validation against physical hardware. Perform simulation and extraction of board models for both SI and PI.
• Contribute to design and sign-off with internal and external ASIC packaging teams, ODMs, and internal layout teams. Create design specifications, work with external vendors, and drive adoption of new interconnect and packaging technologies.
• Actively participate in design reviews, providing insight from your SI/PI expertise and a broader system perspective.
• Support post-silicon bring-up and help troubleshoot production and field failures related to signal and power integrity. Document design processes and provide training/knowledge sharing to other team members.

What You Will Learn

• How to work at the cutting edge of high-speed interconnects, influencing the next generation of ASIC packaging and PCB architectures.
• Deep exposure to advanced ASIC packaging flows and collaboration models with internal and external packaging teams.
• Hands-on experience with emerging high-speed connector technologies and materials, including evaluating material trade-offs for performance and manufacturability.
• Best practices for end-to-end SI/PI validation, from simulation through to lab correlation, post-silicon bring-up, and field failure analysis.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Job Description:

As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university.
• 2+ years of experience supporting or developing complex analog IC designs.

Required Experience:

• Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must
• Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits
• Solid track-record for implementation of analog circuits high-speed data transmission.
• Design and tapeout experience in advanced CMOS nodes (ex. 20nm or newer) is a must
• Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.
• Knowledge of TIA design and drivers for optical applications is highly desirable
• Experience in RFIC design for wireless or wireline communication systems is highly desirable.
• Strong technical independent contributor with a proven ability to drive results.
• Excellent teamwork, presentation, and documentation skills.
• Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.
• Strong experience in lab chip bring-up and debugging efforts.

Preferred Experience:

• Relevant research publications and/or patents in analog or RF IC design.
• Familiarity in programming/scripting languages such as Python, Matlab, or C.
• Experience with PCB design.
• Familiarity with Verilog RTL or DSP design concepts.
• Knowledge of optical transceivers.
• Expertise in ESD protection techniques and IC packaging methodologies.

The base salary range is $150,000.00 USD – $200,000.00 USD.

The base salary range for this role in Canada is $110,000 CAD - $130,000 CAD

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

Job Description:

As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Master’s or PhD degree in EE is required, preferably from a top-tier university.
• 8+ years of experience supporting or developing complex analog IC designs.

Required Experience:

• Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must
• Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits
• Solid track-record for implementation of analog circuits high-speed data transmission.
• Design and tape out experience in advanced CMOS nodes (ex. 7nm, 5nm 3nmFinFET) is a must.
• Solid fundamentals in detailed transistor-level design, feedback/stability analysis, and noise/jitter analysis.
• Knowledge of TIA design and drivers for optical applications is highly desirable
• Experience in RFIC design for wireless or wireline communication systems is highly desirable.
• Strong technical independent contributor with a proven ability to drive results.
• Excellent teamwork, presentation, and documentation skills.
• Ability to collaborate with global teams across multiple time zones and deliver under pressure with strict deadlines.
• Strong experience in lab chip bring-up and debugging efforts.

Preferred Experience:

• Relevant research publications and/or patents in analog or RF IC design.
• Familiarity in programming/scripting languages such as Python, Matlab, or C.
• Experience with PCB design.
• Familiarity with Verilog RTL or DSP design concepts.
• Knowledge of optical transceivers.
• Expertise in ESD protection techniques and IC packaging methodologies.

 Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

As an Analog Architect, you will spearhead pathfinding efforts and work on early prototypes of innovative analog and mixed-signal solutions for Lighmatter’s next-generation optical-engine products. You will then work closely with the engineering team to take your ideas to high-volume production. This role requires a deep understanding of high-frequency systems-on-chip (SoCs), high-speed (100+ Gbaud) serial and electro-optic interfaces. The role also requires creativity, analytical skills, and clear communication skills. You may represent the company at technical conferences as an example of our technical leadership. 

Join a tight-knit team where each individual’s contributions directly influence the success of the company and product. You'll have the opportunity to build a new kind of computer from the ground up and to solve groundbreaking challenges along the way. Work with people who love to build and who thrive in technically diverse environments where great ideas are prioritized.

Responsibilities

• Architect high-speed (200Gbaud and beyond) electro-optical interfaces for Lightmatter’s next-generation co-packaged optics (CPO) solutions.
• Design next-generation high-speed DACs, linear drivers and TIAs in the latest FinFET process nodes.
• Actively collaborate across disciplines—with electronics, photonics, and mechanical engineering teams—to specify the requirements and solutions for circuit blocks, SoCs, debug, and validation.
• Collaborate with the product team to develop our future technological and product roadmap in the context of industry trends.
• Work closely with test and validation engineers to validate hardware against simulation prediction to ensure high performance and high yield.
• Publish and present novel ideas and participate in premier technical conferences.
  
  

Qualifications

• A Ph.D. degree in Electrical Engineering or similar discipline with at least 5+ years of experience of designing high-speed analog circuits in TSMC N3/N5/N7.
• Hands-on experience in high-speed SERDES design in advanced process nodes (7nm and below).
• Deep technical background and a proven track record of innovation in their area of expertise.
• Strong understanding of how the layout impacts the SERDES performance.
• Familiarity with analyzing the impact of package and PCB on SERDES performance.
• Familiarity with UCIe, PAM4, and other high-speed SerDes.
• Strong background with using circuit and electromagnetic simulation tools needed for high-speed mixed-signal circuit design: Cadence virtuoso, Verilog-A, EMX or equivalent tools.

#LI-FM1

As an Analog Architect, you will spearhead pathfinding efforts and work on early prototypes of innovative analog and mixed-signal solutions for Lighmatter’s next-generation optical-engine products. You will then work closely with the engineering team to take your ideas to high-volume production. This role requires a deep understanding of high-frequency systems-on-chip (SoCs), high-speed (100+ Gbaud) serial and electro-optic interfaces. The role also requires creativity, analytical skills, and clear communication skills. You may represent the company at technical conferences as an example of our technical leadership. 

Join a tight-knit team where each individual’s contributions directly influence the success of the company and product. You'll have the opportunity to build a new kind of computer from the ground up and to solve groundbreaking challenges along the way. Work with people who love to build and who thrive in technically diverse environments where great ideas are prioritized.

Responsibilities

• Architect high-speed (200Gbaud and beyond) electro-optical interfaces for Lightmatter’s next-generation co-packaged optics (CPO) solutions.
• Design next-generation high-speed DACs, linear drivers and TIAs in the latest FinFET process nodes.
• Actively collaborate across disciplines—with electronics, photonics, and mechanical engineering teams—to specify the requirements and solutions for circuit blocks, SoCs, debug, and validation.
• Collaborate with the product team to develop our future technological and product roadmap in the context of industry trends.
• Work closely with test and validation engineers to validate hardware against simulation prediction to ensure high performance and high yield.
• Publish and present novel ideas and participate in premier technical conferences.
  
  

Qualifications

• A Ph.D. degree in Electrical Engineering or similar discipline with at least 5+ years of experience of designing high-speed analog circuits in TSMC N3/N5/N7.
• Hands-on experience in high-speed SERDES design in advanced process nodes (7nm and below).
• Deep technical background and a proven track record of innovation in their area of expertise.
• Strong understanding of how the layout impacts the SERDES performance.
• Familiarity with analyzing the impact of package and PCB on SERDES performance.
• Familiarity with UCIe, PAM4, and other high-speed SerDes.
• Strong background with using circuit and electromagnetic simulation tools needed for high-speed mixed-signal circuit design: Cadence virtuoso, Verilog-A, EMX or equivalent tools.

#LI-FM1