Perl Jobs in Colorado.
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Static Timing Analysis (STA) Methodology Engineer
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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is looking for a STA methodology engineer who owns timing across advanced-node, high-performance, low-power designs, bringing deep expertise with PrimeTime, noise/crosstalk/OCV analysis, and strong scripting skills. They will lead the development and optimization of end-to-end STA methodologies and flows, drive data- and ML-assisted timing automation, and partner closely with logic, physical design, DFT, and EDA vendors to solve complex timing challenges across multiple IPs and products.
This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Fort Collins, CO.
We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting
Who you are
- An experienced Static Timing Analysis (STA) / timing methodology engineer with a BS/M in Electrical or Computer Engineering (or equivalent experience) 5+ years in industry, focused on high-performance and low-power designs at advanced technology nodes. As well as a deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
- You are fluent with PrimeTime and related signoff tools (e.g., PT-SI, PTPX, PT-ECO) and have extensive hands-on experience driving signoff correlation, advanced static timing analysis, and signoff closure.
- You are strong at debugging timing constraints, resolving timing correlation issues, and developing effective timing closure strategies.
- You write robust, production-quality scripts in Tcl, Python, and/or Perl and are comfortable building and maintaining CAD utilities and flow components.
What we need
- A senior methodology owner to lead cross-functional efforts to solve complex timing challenges across multiple IPs, projects, and technology nodes. Experience developing and enhancing STA methodologies across the full RTL-to-GDS flow, including: Early timing estimation and timing feasibility checks. Timing optimization techniques in synthesis and place-and-route. Timing signoff methodologies and criteria. Post-route timing ECO strategies and execution.
- A technical leader to architect, optimize, and maintain production STA flows using industry-standard EDA tools, continuously improving PPA (Power, Performance, Area) and runtime efficiency.
- A methodology engineer who can explore and deploy data-driven and ML-assisted techniques to: Improve STA automation. Predict and prioritize timing risk. Guide optimization strategies across blocks and full-chip. Design, implement, and maintain scalable CAD utilities and STA flow components that improve PPA, robustness, and team productivity.
- A methodology owner who continuously refines workflows and introduces new technologies to ensure robust, PPA-optimized timing solutions across all product lines.
What you will learn
- How to scale STA methodologies across a diverse portfolio of IP and SoC programs, balancing aggressive performance targets with strict power and area constraints.
- Best practices for integrating data-driven and ML-assisted approaches into timing flows to improve automation, predictability, and decision-making.
- How to influence tool roadmaps by partnering closely with leading EDA vendors on advanced-node timing, noise, and variability challenges.
- How to operate within and help shape a rapidly evolving startup design environment, including tradeoffs between quick solutions and long-term methodology investments.
- Deeper cross-functional insight into how logic design, physical design, and DFT interact with STA methodology, and how to build flows that serve all of these stakeholders effectively.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Ready to apply?
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Physical Design Engineer
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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.
This role is hybrid, based out of Austin, TX or Santa Clara, CA or Fort Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
- Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
- Strong problem solver who excels at debugging complex issues across design hierarchies.
- Collaborative team player who thrives in fast-paced, technically challenging environments.
What We Need
- BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs.
- Expertise with industry-standard tools (FusionCompiler, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python).
- Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling).
- Experience driving physical design requirements from early architecture through final signoff.
What You Will Learn
- How to implement cutting-edge AI accelerators, high-performance CPUs and the SOCs that host them on the most advanced process nodes.
- Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures.
- End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams.
- Direct impact on products that are redefining the landscape of AI and high-performance computing.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Ready to apply?
Apply to Tenstorrent
Physical Design Engineer - STA
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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We’re looking for a Timing Engineer to join our silicon team. In this role, you’ll drive static timing analysis and closure for complex, high-performance designs. You’ll collaborate closely with logic, DFT, and physical design teams to debug constraints, optimize paths, and ensure our chips meet performance targets across corners and modes.
This role is hybrid, based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- Experienced in STA and passionate about enabling silicon to meet aggressive performance goals.
- Analytical and detail-oriented, with a strong understanding of timing paths, constraints, and optimization strategies.
- A collaborative team player who works well across logic, DFT, and physical design boundaries.
- Resourceful and self-driven, capable of developing scripts and methodologies that improve timing closure workflows.
What We Need
- 7+ years of industry experience and a proven record of successful tapeouts.
- Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
- Proficiency in writing and debugging SDC constraints, creating ECOs, and developing closure strategies.
- Strong scripting skills in Python, Perl, and TCL to support automation and flow development.
- Familiarity with SPICE modeling and worst-case corner analysis.
What You Will Learn
- How to close timing on Tenstorrent’s high-performance RISC-V CPUs and AI SoCs.
- Advanced STA methodologies tailored to modern sub-micron process technologies.
- How to collaborate with world-class engineers across RTL, DFT, and physical design teams.
- How to influence chip performance through timing methodology innovation and automation.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Ready to apply?
Apply to Tenstorrent
Staff Engineer, Physical Design
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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team.
This role is hybrid, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts.
- Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration.
- Strong problem solver who excels at debugging complex issues across design hierarchies.
- Collaborative team player who thrives in fast-paced, technically challenging environments.
What We Need
- BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs.
- Expertise with industry-standard tools (Innovus, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python).
- Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling).
- Experience driving physical design requirements from early architecture through final signoff.
What You Will Learn
- How to implement cutting-edge AI accelerators and high-performance CPUs on the most advanced process nodes.
- Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures.
- End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams.
- Direct impact on products that are redefining the landscape of AI and high-performance computing.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Ready to apply?
Apply to Tenstorrent
Staff Physical Design Engineer – EMIR
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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We’re looking for a Physical Design Engineer – EMIR to join our silicon team. In this role, you’ll lead EM and IR-drop simulations to ensure robust power delivery, signal integrity, and long-term reliability for high-performance ICs. You’ll work with RTL, physical design, and analysis teams to implement power grid strategies that optimize performance, power, and area (PPA), particularly at advanced nodes like 7nm and below. You’ll also support EMIR sign-off and waiver methodologies across the chip hierarchy.
This role is hybrid, based out of Austin, TX or Santa Clara, CA.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- A physical design specialist with deep experience in EMIR analysis and signoff.
- Comfortable navigating advanced technology nodes and power integrity challenges.
- Proactive and detail-oriented, with a passion for pushing performance and reliability boundaries.
- Collaborative and effective across teams working on RTL, physical design, packaging, and reliability.
What We Need
- 7+ years of experience in physical design or signoff, with a focus on EMIR.
- Hands-on with RedHawk, Voltus, or equivalent industry-standard EMIR tools.
Strong understanding of IR-drop mitigation, EM compliance, and power grid design. - Proficiency with layout extraction flows, RC modeling, and metal density checks.
- Experience working in advanced nodes (7nm, 5nm, 3nm), and with scripting languages like TCL, Python, Perl, or Shell.
- Knowledge of floorplanning, bump/RDL design, and sign-off flows (DRC/LVS, timing closure).
What You Will Learn
- How to architect and analyze robust power delivery for Tenstorrent’s RISC-V CPUs and AI chips.
- How to integrate EMIR signoff into fast-paced, high-performance chip design cycles.
- Best practices for hierarchical analysis and EMIR methodology across pre- and post-layout flows.
- Cross-functional collaboration for optimizing PPA while meeting stringent reliability goals.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
Ready to apply?
Apply to Tenstorrent
Partner Solutions Architect (Public Sector)
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We are Datadog's in-house product experts. The technical solutions team enables Datadog's worldwide growth by educating potential clients and ensuring that existing customers are happy and successful.
The Partner Solution Architect (PSA) is a Datadog expert who will work closely with Datadog’s Director of Partner Solutions Architects, and is aligned to our Channels & Alliances business segment. The PSA is responsible for supporting a variety of technical initiatives and activities for our partners (for example: cloud migration, application modernization, DevOps transformation). They are accountable for the outcome of these initiatives, and frequently collaborate with both Datadog and Partner resources to drive success. The PSA is a trusted technical advisor for our Partner channel.
At Datadog, we place value in our office culture - the relationships and collaboration it builds and the creativity it brings to the table. We operate as a hybrid workplace to ensure our Datadogs can create a work-life harmony that best fits them.
What You’ll Do:
- Ensure the successful onboarding, training, enablement, and certification of partner technical resources;
- Participate in periodic joint business planning and review sessions to ensure direct alignment between Datadog and Partner technical teams;
- Collaborate internally to support Partner technical initiatives such as end-customer demonstrations and proofs of value; partner team enablement workshops; assessment, advice, and coaching on lead practices;
- Advocate on behalf of Partners’ technical concerns (use cases, feature requests, support issues, e.g.) with Datadog internal teams and personnel, helping to bring those concerns to resolution;
- Analyze and understand Partner service offerings on a regular basis and provide recommendations to enhance the value of those services through greater or improved adoption of Datadog features and capabilities;
- Collaborate with Datadog’s product management, engineering and technical services teams to help identify and prioritize new features and capabilities;
- Continuously help curate and evolve lead/best practices for Datadog platform adoption and success.
Who You Are:
- Possess a solid technical grounding with hands-on experience of IT Development and/or Operations
- Has a demonstrable track-record and never-ending passion for learning; successful candidates for this position typically have 10-15 years of experience in a customer or partner facing technical role
- A self-starter, tech-savvy professional with solid business acumen; ability to articulate Datadog value from server room to boardroom;
- Confident presentation skills
- Desired hands-on experience in two or more of the following areas:
- Observability: Datadog, Splunk, AppD, New Relic or Dynatrace
- Public Cloud: AWS, Azure, GCP, or Alibaba
- Containerization: Docker, Kubernetes, OpenShift, Cloud Foundry
- Dev/Scripting: Python, Javascript, Ruby, Perl, PHP, Go
- Config Mgmt: Terraform, Ansible, Puppet, Chef
- CI / CD: Jenkins, Gitlab
- Bonus Points:
- Previous experience working in a technical role for or supporting channel partners (Systems Integrators, Managed Services Providers, e.g.)
- Previous experience using Datadog and/or other cloud monitoring tools (APM,
- Infrastructure, Logs, Synthetics, NPM)
- Previous experience with root-cause-analysis, troubleshooting, debugging
Datadog values people from all walks of life. We understand not everyone will meet all the above qualifications on day one. That's okay. If you’re passionate about technology and want to grow your skills, we encourage you to apply.
Benefits and Growth:
- Best-in-breed onboarding
- Generous global benefits
- Intra-departmental mentor and buddy program for in-house networking
- New hire stock equity (RSUs) and employee stock purchase plan (ESPP)
- Continuous professional development, product training, and career pathing
- An inclusive company culture, able to join our Community Guilds and Inclusion Talks
Benefits and Growth listed above may vary based on the country of your employment and the nature of your employment with Datadog.
Datadog offers a competitive salary and equity package, and may include variable compensation. Actual compensation is based on factors such as the candidate's skills, qualifications, and experience. In addition, Datadog offers a wide range of best in class, comprehensive and inclusive employee benefits for this role including healthcare, dental, parental planning, and mental health benefits, a 401(k) plan and match, paid time off, fitness reimbursements, and a discounted employee stock purchase plan.
About Datadog:
Datadog is the leading observability and security platform for the AI era, providing businesses with unified visibility across the technology stack to manage complexity at scale. It brings applications, infrastructure, data, models, and security into one place, using AI to detect and resolve issues before they impact customers. Trusted globally by Fortune 500 companies and high-growth AI leaders, Datadog enables businesses to move faster with clarity and confidence. Learn more about #DatadogLife on Instagram, LinkedIn, and Datadog Learning Center.
Equal Opportunity at Datadog:
Datadog is proud to offer equal employment opportunity to everyone regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity, veteran status, and other characteristics protected by law. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. Here are our Candidate Legal Notices for your reference.
Datadog endeavors to make our Careers Page accessible to all users. If you would like to contact us regarding the accessibility of our website or need assistance completing the application process, please complete this form. This form is for accommodation requests only and cannot be used to inquire about the status of applications.
Privacy and AI Guidelines:
Any information you submit to Datadog as part of your application will be processed in accordance with Datadog’s Applicant and Candidate Privacy Notice. For information on our AI policy, please visit Interviewing at Datadog AI Guidelines.
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