The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Implementation of DFT features into RTL using verilog.
• Understanding of DFT Architectures and micro-architectures.
• ATPG and test coverage analysis using industry standard tools.
• JTAG, Scan Compression, and ASST implementation.
• Gate level simulation using Synopsys VCS and Verdi.
• Support silicon bring-up and debug.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Develop efficient DFx flows and methodology compatible with front end and physical design flows

Experience & Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques.
• DFx experience implementing in finFET technologies.
• Experience with industry standard ATPG and DFx insertion CAD tools.
• Familiarity with SystemVerilog and UVM.
• Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
• Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
• Good understanding of high-performance, low-power design fundamentals.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Experience with Fault Campaigns a plus.
• Strong problem solving and debug skills across various levels of design hierarchies.

Principal Embedded SW/FW Engineer (Bringup) - Bengaluru, multiple vacancies 

Job Summary

We have an exciting opportunity to be part of a collaborative, cross-functional development team validating cutting-edge, high-performance AI chips and platforms.

 You will play a key role in supporting new product introductions and post-silicon validation.

Working within the Post-Silicon Validation team, you will be involved with bringing first silicon to life, functionally validating it and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to provide technical guidance to other engineering team members. In this role, you can leverage our experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes.

The Team

The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team.

Responsibilities and Duties

• Plan, design, develop and debug silicon validation tests in bare metal C/C++ on FPGA/Emulator prior to first silicon
• Deploy silicon validation tests on first silicon and debugging them
• Develop automated test framework and regression test suites in Python to optimize validation efficiency
• Collaborate closely with engineers from many other disciplines on a variety of topics
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies
• Analyse test results, identify and debug failures/defects
• Contribute to shared test and validation infrastructure
• Provide feedback to architects

Candidate Profile 

Essential:

• Understanding of ML applications and their workloads
• A self-starter who can apply independent judgement
• A team player able to lead and support colleagues with difficult concepts
• Strong experience in Bare metal / embedded C/C++

• Excellent problem-solving, analytical & diagnostic skills

• Ability to work across teams and programming languages to find root causes of critical and complex issues

• Experience of the post-silicon validation process applied in digital ASIC environments

• Python, Linux

• Excellent communication skills and the ability to explain difficult concepts to resolve issues 

Desirable

• 10+ years  experience 
• Experience building and leading, multi-site teams
• Driver level experience with one or more of the following is highly desirable:

• PCIe
• Ethernet
• Memory technologies (LPDDR, DDR, HBM, …)
• Other peripherals such as I2C, I3C, SPI, …

• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable.
• Experience of Arm CPUs, System IP and debug tools.
• Experience of AMBA protocols.
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, 

Silicon Verification Engineer

Multiple roles across different levels

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:
• Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Staff Embedded SW/FW Engineer (Bringup)

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption.  

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.

Job Summary

We have an exciting opportunity to be part of a collaborative, cross-functional development team developing C code used to validate cutting-edge, high-performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation.

Working within the Post-Silicon Bringup team, you will be involved with bringing first silicon to life, developing code primarily in C to configure and exercise systems and sub-systems on new silicon devices, and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes.

The Team

The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. 

Responsibilities and Duties

• Plan, design, develop and debug silicon bringup sequences and test in bare metal C/C++ on FPGA/Emulator prior to first silicon
• Deploy configuration sequences and validation tests on first silicon and debug them
• Develop automated test framework and regression test suites in Python to optimize validation efficiency
• Collaborate closely with engineers from many other disciplines on a variety of topics
• Work with Validation and Production Test engineering peers to implement best practices and continuous improvements to test methodologies
• Analyse test results, identify and debug failures/defects
• Contribute to shared test and validation infrastructure
• Provide feedback to architects

Candidate Profile

Essential:

• Strong experience in Bare metal / embedded C/C++
• Good knowledge of digital ASICs.
• Be highly motivated, a self starter, and a team player 
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the post-silicon validation process applied in digital ASIC environments
• Python, Linux
• Excellent communication skills and the ability to collaborate with others to solve problems.
• Excellent problem-solving, analytical & diagnostic skills

Desirable:

• Driver level experience with one or more of the following is highly desirable:

• PCIe
• Ethernet
• Memory technologies (LPDDR, DDR, HBM, …)
• Other peripherals such as I2C, I3C, SPI, …

• Good knowledge of mixed-signal building blocks such as PLLs, high speed PHYs and IC control/communication protocols is highly desirable.
• Experience of Arm CPUs, System IP and debug tools.
• Experience of AMBA protocols.
• Understanding of ML applications and their workloads.
• Experience in Characterization, Failure Analysis, Test Development, Statistical analysis, and Customer Support

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

Silicon Verification Engineer

Multiple roles across different levels

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. 

As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing.  

The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery.

Responsibilities

• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure
• Ensuring good communication between sites

Essential skills:

•8 to 12 Years of experience
•Verification experience in relevant industry
• Proven leadership and planning skills
• Highly motivated, a self starter, and a team player
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux

Desirable skills:
• UVM
• SVA
• Assembly languages
• LLVM, GCC
• DVCS e.g. Git
• SGE or other DRMS
• XML and XPath/XSLT
• Web programming – HTML/DOM, Javascript, SQL  

Benefits:

In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. 

The Role:
In this exciting role, you will be responsible for bring up and optimizations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have experience delivering end to end solutions working closely with teams across chip design, system performance, software development and productization.

Responsibilities:

• On Wafer Scale Engines, develop and debug flows that embed well tested and deployable optimizations in production processes to reduce time and costs 
• Work on refining AI Systems across H/W-S/W design constraints such as di/dt, V-F characterization space, current and temperature limits in relation to optimizations for performance.
• Develop/Enhance infrastructure to enable silicon for real world workload testing
• Develop self-checking metrics, as well as instrumentation for debug and coverage
• Work with the silicon architects/designers, performance engineers and software engineers to enhance performance of Wafer Scale Engines.
• Work across domains such as, Software, Design, Verification, Emulation & Validation to refine and optimize performance and process.
• Work with CI/CD tools, git repositories, github, git actions/Jenkins, merge and release flows to streamline test and release.

Skills & Qualifications:

• BS/BE/B.Tech or MS/M.Tech in EE, ECE, CS or equivalent work experience
• 7-10+ years of industry experience
• 3-5 years of experience in Pre-silicon & Post Silicon ASIC hardware
• Good understanding of computer architecture and networking
• Excellent Coding in languages such as Python/Verilog/System Verilog and C
• Proficient in hardware/software codesign and layered architectures.
• Excellent debugging, analytical, and problem-solving skills
• Proficient in large scale testing and automation using pytest and python
• Good presentation skills to refine diverse information and put forth optimization strategies and results.
• Good interpersonal skills, ability & desire to work as a standout colleague
• Proven track record of working cross-functionally learning fast and driving issues to closure 

Preferred:

• Previous work in AI-ML with 100+ CPU core & communication fabric-based design.
• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
• Knowledge of chip defect profiles and mitigation strategies across the hardware and software stack
• Familiarity in creating test and s/w infrastructure at large scale
• Working across global time zones 

Location:
Bangalore, India

Toronto, Canada

Sunnyvale, California.

For Sunnyvale: The base salary range for this position is $175,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

The Role 

We are seeking a highly skilled and motivated Manufacturing Bring-up Engineer to join our team. As the Manufacturing Bring-up Engineer you will support our system level bring-up process execution, implementation, and evolution in the manufacturing pipeline. This is a high visibility role that requires strong technical expertise, coordination, and collaboration to deliver our product from manufacturing to the customer. 

Responsibilities 

• Support the Cerebras manufacturing bring-up process execution to configure, test, and validate system performance prior to customer shipment 

• Collaborate cross-functionally with Asic, SW, Diagnostics, and QA teams to further automate and streamline the workflow for optimal manufacturing efficiency 

• Troubleshoot and resolve technical issues during system bring-up across Asic, SW, and QA domains 

• Design and implement efficient processes to manage and track system bring-up status and progress 

• Track and report on critical bring-up metrics to drive continuous improvement  

• Implement further SW automation and efficiencies to effectively scale the manufacturing bring-up process in support of the manufacturing roadmap 

Skills & Qualifications 

• BS or MS in EE, ECE, CS or equivalent work experience 

• 3+ years of industry experience in an operations environment 

• Experience in hardware bring-up and the debug of complex systems 

• Working knowledge and experience in Asic bringup and test processes 

• Working knowledge of scripting in languages such as Python and/or Perl 

• Proven experience in system bring-up and validation of complex computer systems or equivalent technologies 

• Understanding of computer system architecture and hardware components  

• Proficiency in scripting and automation tools for system bringup  

• Excellent problem-solving and communication skills with the ability to work collaboratively in a fast-paced environment 

• Very strong coordination and collaboration skills to manage a business-critical workflow directly in support of customer demand 

Preferred: 

• Familiarity in creating test and s/w infrastructure at large scale 

• Working across global time zones  

Location 

Bangalore, India/Toronto, Canada/ Sunnyvale, California.

The base salary range for this position is $170,000 to $230,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

The Role 

We are seeking a highly skilled and motivated Manufacturing Bring-up Engineer to join our team. As the Manufacturing Bring-up Engineer you will support our system level bring-up process execution, implementation, and evolution in the manufacturing pipeline. This is a high visibility role that requires strong technical expertise, coordination, and collaboration to deliver our product from manufacturing to the customer. 

Responsibilities 

• Support the Cerebras manufacturing bring-up process execution to configure, test, and validate system performance prior to customer shipment 

• Collaborate cross-functionally with Asic, SW, Diagnostics, and QA teams to further automate and streamline the workflow for optimal manufacturing efficiency 

• Troubleshoot and resolve technical issues during system bring-up across Asic, SW, and QA domains 

• Design and implement efficient processes to manage and track system bring-up status and progress 

• Track and report on critical bring-up metrics to drive continuous improvement  

• Implement further SW automation and efficiencies to effectively scale the manufacturing bring-up process in support of the manufacturing roadmap 

Skills & Qualifications 

• BS or MS in EE, ECE, CS or equivalent work experience 

• 3+ years of industry experience in an operations environment 

• Experience in hardware bring-up and the debug of complex systems 

• Working knowledge and experience in Asic bringup and test processes 

• Working knowledge of scripting in languages such as Python and/or Perl 

• Proven experience in system bring-up and validation of complex computer systems or equivalent technologies 

• Understanding of computer system architecture and hardware components  

• Proficiency in scripting and automation tools for system bringup  

• Excellent problem-solving and communication skills with the ability to work collaboratively in a fast-paced environment 

• Very strong coordination and collaboration skills to manage a business-critical workflow directly in support of customer demand 

Preferred: 

• Familiarity in creating test and s/w infrastructure at large scale 

• Working across global time zones  

Location 

Sunnyvale, California/ Bangalore, India/Toronto, Canada.

The base salary range for this position is $170,000 to $230,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

The Role:
In this exciting role, you will be responsible for bring up and optimizations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have experience delivering end to end solutions working closely with teams across chip design, system performance, software development and productization.

Responsibilities:

• On Wafer Scale Engines, develop and debug flows that embed well tested and deployable optimizations in production processes to reduce time and costs 
• Work on refining AI Systems across H/W-S/W design constraints such as di/dt, V-F characterization space, current and temperature limits in relation to optimizations for performance.
• Develop/Enhance infrastructure to enable silicon for real world workload testing
• Develop self-checking metrics, as well as instrumentation for debug and coverage
• Work with the silicon architects/designers, performance engineers and software engineers to enhance performance of Wafer Scale Engines.
• Work across domains such as, Software, Design, Verification, Emulation & Validation to refine and optimize performance and process.
• Work with CI/CD tools, git repositories, github, git actions/Jenkins, merge and release flows to streamline test and release.

Skills & Qualifications:

• BS/BE/B.Tech or MS/M.Tech in EE, ECE, CS or equivalent work experience
• 7-10+ years of industry experience
• 3-5 years of experience in Pre-silicon & Post Silicon ASIC hardware
• Good understanding of computer architecture and networking
• Excellent Coding in languages such as Python/Verilog/System Verilog and C
• Proficient in hardware/software codesign and layered architectures.
• Excellent debugging, analytical, and problem-solving skills
• Proficient in large scale testing and automation using pytest and python
• Good presentation skills to refine diverse information and put forth optimization strategies and results.
• Good interpersonal skills, ability & desire to work as a standout colleague
• Proven track record of working cross-functionally learning fast and driving issues to closure 

Preferred:

• Previous work in AI-ML with 100+ CPU core & communication fabric-based design.
• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
• Knowledge of chip defect profiles and mitigation strategies across the hardware and software stack
• Familiarity in creating test and s/w infrastructure at large scale
• Working across global time zones 

Location:

Sunnyvale, California.

Bangalore, India

Toronto, Canada 

The base salary range for this position is $175,000 to $275,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Location:

Hybrid, working onsite at our Bangalore offices 3 days per week.

Minimum:

• BS in Electrical Engineering, Computer Science, or a related field with 8+ years of industry experience, or an MS in Electrical Engineering, Computer Science, or a related field with 7 years of industry experience is preferred.

• Experience in IP/SoC verification cycle preferably from concept to tape-out to bring-up.

• Good knowledge of verification methodologies such as UVM/OVM, etc.

• Hands-on ASIC-SoC design verification tests and debug experience.

• Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology.

• Good problem-solving skills and the passion to take on challenges (particularly in AI domain).

• Passionate about AI and thriving in a fast-paced and dynamic startup culture.

Preferred:

• Part of Successful implementation of multiple verification environments and tape-out efforts.

• Experience with C/C++ is good