This role is for one of the Weekday's clients

Salary range: Rs 2400000 - Rs 2600000 (ie INR 24-26 LPA)

Experience: 6+ yrs

Location: Bengaluru

Job Type: Full-Time

We are seeking an experienced IO IP Design Engineer to lead the development of high-performance IO intellectual property (IP) solutions across multiple semiconductor technology nodes. In this role, you will be responsible for the complete lifecycle of IO IP development, including architecture definition, analog and mixed-signal circuit design, simulation, verification, reliability analysis, and silicon validation. You will collaborate with cross-functional engineering teams to deliver robust, power-efficient, and high-quality IO solutions while driving innovation and ensuring successful product execution.

Requirements

Key Responsibilities

• Design, develop, and deliver high-performance IO IPs such as GPIO, LVDS, SSTL, HSTL, MIPI, and other interface standards across multiple technology nodes.
• Define IO IP architecture and develop analog and mixed-signal circuit designs that meet performance, power, area (PPA), and reliability targets.
• Perform transistor-level circuit design, simulation, optimization, and verification to ensure functional accuracy and robust operation.
• Conduct comprehensive reliability verification, including performance validation across process, voltage, temperature (PVT), and corner conditions.
• Collaborate with layout engineers to ensure high-quality physical implementation, layout optimization, and first-pass silicon success.
• Support the design and implementation of test chips, package design, evaluation boards, and post-silicon validation activities.
• Participate in silicon characterization, debugging, qualification, and performance optimization after fabrication.
• Work closely with cross-functional teams including Layout, Verification, Packaging, Product Engineering, and Validation throughout the product development lifecycle.
• Contribute to product planning by participating in market analysis, technology evaluation, and product definition activities.
• Mentor layout engineers and promote best practices in analog and mixed-signal design methodologies.
• Drive continuous innovation by evaluating new technologies, improving design methodologies, and enhancing overall IP development efficiency.

What Makes You a Great Fit

• Strong hands-on experience in IO IP Design, including technologies such as GPIO, LVDS, SSTL, HSTL, MIPI, or similar high-speed interface standards.
• Expertise in Analog and Mixed-Signal Circuit Design, simulation, optimization, and performance analysis.
• Strong understanding of transistor-level circuit design, analog simulation, and reliability verification methodologies.
• Experience with performance, power, area (PPA) optimization across multiple semiconductor technology nodes.
• Hands-on experience supporting silicon validation, characterization, post-silicon debugging, and qualification activities.
• Ability to collaborate effectively with layout, verification, packaging, and product engineering teams throughout the chip development lifecycle.
• Experience supervising or mentoring layout engineers while ensuring high-quality design execution.
• Strong analytical, debugging, and problem-solving skills with attention to performance, reliability, and manufacturability.
• Excellent communication and collaboration skills with the ability to work in multidisciplinary engineering environments.
• A proactive mindset with a passion for innovation, continuous improvement, and delivering high-quality semiconductor IP solutions.