This role is for one of the Weekday's clients

Salary range: Rs 2700000 - Rs 4000000 (ie INR 27- 40 LPA)

Min Experience: 9+ years

Location: Bengaluru
JobType: full-time

We are seeking an experienced Analog Layout Engineer with 9–12 years of hands-on experience in custom analog and mixed-signal IC layout development. The ideal candidate will possess deep expertise in GF 65nm technology, PLL (Phase-Locked Loop) layouts, and high-performance analog layout design. In this role, you will collaborate closely with circuit designers, verification engineers, and physical design teams to develop robust, high-quality layouts that meet stringent performance, reliability, and manufacturability requirements.

This is an excellent opportunity for engineers passionate about advanced semiconductor design and committed to delivering high-quality analog IP for cutting-edge products.

Requirements

Key Responsibilities

• Design and implement custom analog and mixed-signal layouts using GF 65nm process technology.
• Develop complex layouts for PLL blocks, including VCOs, charge pumps, loop filters, frequency dividers, bias circuits, and associated analog components.
• Translate circuit schematics into optimized physical layouts while ensuring compliance with process design rules and design specifications.
• Perform floorplanning, device matching, routing, shielding, guard ring implementation, and substrate isolation techniques to achieve superior circuit performance.
• Execute DRC, LVS, ERC, and parasitic extraction checks and work closely with design teams to resolve layout-related issues.
• Optimize layouts for area, performance, yield, reliability, and manufacturability.
• Collaborate with circuit designers during layout reviews and support post-layout simulations by addressing parasitic concerns.
• Apply best practices for common-centroid layouts, symmetry, matching, electromigration, and IR-drop considerations.
• Participate in design reviews and contribute to continuous improvements in layout methodologies and design flows.
• Mentor junior layout engineers by sharing technical expertise and reviewing layout quality.

Required Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or a related discipline.
• 9–12 years of professional experience in analog and mixed-signal layout design.
• Strong expertise in Analog Layout for advanced semiconductor products.
• Extensive hands-on experience with GF 65nm technology.
• Proven experience designing and optimizing PLL layouts for high-performance applications.
• Strong understanding of semiconductor fabrication processes and physical verification methodologies.
• Proficiency in industry-standard EDA tools such as Cadence Virtuoso Layout Suite or equivalent.
• Experience performing DRC, LVS, ERC, and parasitic extraction using industry-standard verification tools.
• Solid understanding of layout matching techniques, shielding, guard rings, latch-up prevention, ESD considerations, and substrate noise isolation.
• Ability to interpret circuit schematics and collaborate effectively with analog circuit designers.

Must-Have Skills

• GF 65nm Technology
• PLL Layout Design
• Analog Layout
• Custom Analog & Mixed-Signal Layout
• Cadence Virtuoso
• DRC/LVS/ERC Verification
• Device Matching Techniques
• Parasitic-Aware Layout Optimization

Preferred Skills

• Experience with RF or high-speed mixed-signal layouts.
• Knowledge of reliability analysis, electromigration, and IR-drop optimization.
• Familiarity with scripting languages such as SKILL, Perl, Python, or Tcl for layout automation.
• Experience supporting silicon bring-up and layout debugging.
• Exposure to multiple semiconductor process nodes and foundry technologies.