About the Role 
ADI’s Aerospace and Defense Sensors, Subsystems, & Space business unit has an open position for an experienced Staff Digital Design Engineer with a background in FPGA/ASIC RTL and schematic capture. Working on new technology development, you will design cutting-edge integrated modules and subsystems for electronic warfare (EW), communication, and phased array radar systems.  In this position, you will interface with staff involved with design, testing, manufacturing engineering, program management, business development, and division management throughout all program phases of research, design, and production. 

This position requires deep expertise across multiple technical domains and strong cross-functional collaboration skills to drive innovation and excellence in digital design. 

 
Key Responsibilities 

• Develop FPGA-based designs for digital data and control paths leveraging ADI high-speed converters, including schematic, RTL, simulation, analysis, and interface validation 

• Define and develop system-level architectures for complex digital designs 

• Lead technical teams on complex digital design projects 

• Collaborate with multiple teams for new product development, system design, and performance verification of hardware and software 

• Influence product direction and technical roadmaps 

• Engage directly with customers on technical requirements and solutions 

• Mentor engineers and help develop technical talent 

Qualifications 

• *+ years of relevant experience in digital design engineering 

• Expert ability to define and implement complex digital system architectures 

• PCB design, including part selection, schematic capture, debug, and optimization 

• High speed interface design and bring-up and testing, e.g. 100 GigE, Aurora, PCIe 

• Experience with schematic capture and PCB layout tools, e.g. Allegro, PADS 

• Familiarity with high speed PCB layout techniques/concepts 

• Skilled in design techniques that maximize isolation and prevent signal integrity issues. 

• RTL design (Verilog, VHDL), simulation, timing closure in large FPGAs 

• Strong organizational and communications skills with ability to work in a fast-paced & dynamic environment. 

• U.S. citizenship 

• Ability to obtain a Secret Clearance 

 
Preferred Education and Experience 

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent  

• Experience with DOD radar, electronic warfare, or RF communications algorithms 

• Familiarity with C#, Python, C/C++, TCL 

• Familiarity with RF systems 

• Experience with low complexity DC power tree designs and voltage sequencing