NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we're tapping into the unlimited potential of AI to define the next era of computing — an era in which our GPUs act as the brains of computers, robots, and self-driving cars. Doing what's never been done before takes vision, innovation, and the world's best talent. Come join our diverse team and see how you can make a lasting impact on the world.

The Digital IP (DIP) group at NVIDIA develops IP for every chip designed at NVIDIA. This group works closely with internal SOC design, silicon testing, and productization teams that turn our IP into products that change the world. One of the roles fulfilled by the DIP group is to develop sophisticated SRAM compilers that are used extensively by our SOC design partners. We are looking to hire a skilled and creative SRAM circuit designer to help achieve these goals in a high-visibility position.

What you'll be doing:

• Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.
• SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.
• Advanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.
• Guiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications.

What we need to see:

• Master's degree or higher in Electrical Engineer or other related field (or equivalent experience).
• SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET and nanosheet processes.
• Design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits such as self-timed logic and sense-amplifiers.
• Familiarity with Cadence Virtuoso schematic and layout capture tools
• Shown dewlivery of silicon IP into production.

Ways to stand out from the crowd:

• Shown written, verbal, and presentation skills.
• Skills in AI coding and analysis tools such as Codex and Claude Code.
• Silicon testing/debug experience.

NVIDIA is widely considered one of the technology world's most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative, curious, and eager to own something that matters at scale — we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.Applications for this job will be accepted at least until October 17, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.