SR. SILICON PACKAGING PROCESS ENGINEER, SILICON TECHNOLOGY (STARLINK)

SpaceX is leveraging its experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to 4M+ users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact. As we continue to upgrade and expand the constellation, we’re looking for best-in-class engineers to join the team.

In true SpaceX fashion, Starlink is taking the next step in vertical integration by bringing integrated circuit packaging and assembly in-house for development and manufacturing. We are looking for hands-on and dynamic engineers with expertise in semiconductor packaging design, process development, equipment, and test. You will assume full ownership of packaging products and process modules and take them from concept to mass production as we strive to make Starlink more affordable to those who need it most.

RESPONSIBILITIES:  

• Own packaging assembly processes from concept to mass production including equipment and material selection for wafer-level and chip-level systems
• Develop new technologies and establish baselines for assembly and packaging including wafer grinding, wafer dicing, lithography, lamination, plating, etching, SMT, flip chip, bonding, molding, underfill, dispense, sputter, lid attach, and solder ball attach
• Bring-up for new product introduction (NPI) and new technology introduction (NTI) for assembly packaging lines
• Own packaging prototypes, product development and release to production
• Select equipment and material to meet quality, reliability, cost, yield, and production targets
• Interface with equipment and material suppliers including continuous improvement plans, cost reduction, and productivity improvements
• Cross-functional interface with IC design, materials, thermal, systems, and production teams
• Implement advanced packaging solutions into SpaceX next generation products

BASIC QUALIFICATIONS: 

• Bachelor’s degree in electrical engineering, mechanical engineering, chemical engineering, materials science, physics, or other applied engineering discipline  
• 5+ years of professional experience in semiconductor assembly and packaging

PREFERRED SKILLS AND EXPERIENCE: 

• Advanced technical degree
• 7+ years industry experience with microelectronics packaging development
• Packaging familiarity with flip-chip, BGA, fcCSP, WLCSP, fan out FO processes, system-in-package SiP, multi-chip modules MCM, panel level packaging, heterogenous and chiplet integration
• Hands-on packaging, PCB, PCBA, or SMT assembly experience
• OSAT (outsource semiconductor assembly and test) experience a plus