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Job Description:

As an SOC Timing engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing. Candidate will be involved in static timing analysis, providing/deriving interface timing constraints to partitions and doing final timing signoff. Candidate will also work closely with design and architecture team for timing convergence analysis and will also work with physical design team for timing closure. 

Qualifications:

- Proficient in physical design industry standard EDA tools such as Primetime/PTPX 

- Good knowledge of physical design and PNR flow 

- Should have experience in timing signoff in 10nm or lower technology 

- BE/MS/Phd in Electronics/Electrical Engineering with 10+ Years’ experience timing closure and signoff.   

- Candidate should be strong in communication, problem solving and analytical skill 

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