Role Overview
Astera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

As a senior technical leader, you'll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You'll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions.

Key Responsibilities

• Architecture & Technical Leadership
• Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines
• Establish architectural standards and best practices that scale across the design organization
• Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area
• Design Execution & Ownership
• Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up
• Drive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies
• Own accountability for design quality, schedule, and successful production delivery
• Cross-Functional Collaboration
• Partner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues
• Collaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up
• Work with firmware and software teams to optimize hardware-software interfaces
• Mentorship & Process Excellence
• Mentor and develop junior and senior engineers, elevating team technical capabilities
• Drive continuous improvement of silicon development processes, CAD automation, and design infrastructure
• Contribute to organizational knowledge sharing and technical reviews

Basic Qualifications

• Bachelor's degree in Electrical Engineering or equivalent
• 12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
• Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure
• Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar
• Production experience with advanced CMOS nodes (≤7nm)
• Proficiency with Cadence and/or Synopsys digital design flows
• Track record of delivering multiple high-performance designs to production

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Experience with multiple high-speed protocols (PCIe Gen 5/6, CXL, UALink, Ethernet, DDR4/DDR5)
• Hands-on collaboration with embedded firmware teams and familiarity with RISC-V or Arm subsystems
• Proven contributions to design methodology, CAD automation, or infrastructure improvements
• Experience leading technical teams or driving cross-functional initiatives in data center environments

Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.