About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Join Marvell's Custom Compute Solutions Business Unit (CCSBU) as we establish our design presence in San Diego's thriving semiconductor ecosystem.

This team will be responsible for delivering high‑quality customer silicon for advanced AI, XPU, and XPU‑Attach programs. By partnering closely with customers and internal stakeholders, the design center will enable Marvell’s most strategic and financially significant custom SoC initiatives, delivering differentiated solutions that reinforce Marvell’s position as a trusted partner for next‑generation compute platforms.

This is a rare foundational leadership opportunity - you'll shape design strategy from the ground up and build a world-class team as part of our strategic expansion into Southern California. You're not joining an established team - you're building one. You'll hire the engineers, define the culture, establish the methodology, and shape the technical DNA of Marvell's San Diego design organization.

What You Can Expect

As a Senior Director, you’ll be responsible for collaborating with various teams to develop strategies, pushing the IP roadmap, and supporting multiple SOCs. This starts at the product definition phase with architecture and marketing then continues through execution of all efforts required including supporting productization. You’ll provide leadership in the development of highest value-add IP & SOC plans and strategies with cutting edge process, speed and performance designs.

The planning and execution need to be rationalized with budget and market timing requirements.  Experience and judgement in determining the value of the tasks defined and executed by the team is important.  This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology looking for ways to improve the value and quality of the effort while keeping cost in budget.

In this role, you will:

• Manage and continue to build a team of complex sub-system, co-processors, accelerator and SOC engineers. The managed team includes design, verification, and working with the physical design engineers in central engineering.
• Develop methodologies and infrastructure with evolving technology challenges including cutting edge semiconductor process, I/O’s, networking bandwidth, embedded cores, and co-processors.
• Work with architecture, SOCs, software, firmware, program management and post-silicon design teams for plan development and execution.
• Provide technical mentoring for team members.
• Actively engage in efforts to find improvements in methodologies, techniques, and automation.
• Own schedules and reporting of progress metrics.

What We're Looking For

• BS degree or higher in EE or CE or CS15+ years or more of RTL and/or verification experience.
• 5 + years of experience managing a design team.
• Demonstrated ability to lead a multi-disciplinary team, show initiative, and communicate effectively with team members / marketing / other engineering groups.
• Experience in all phases of design from concept through productization
• Demonstrated mentoring of junior staff.
• Ability to recruit and retain engineering talent.

Preferred Qualifications:

• Experience with networking sub-systems.
• Experience developing IP and SOCs.
• Experience with one or more high-speed IO technologies: DDR, PCIe, SATA, USB, Ethernet Management of cross-site teams.
• Experience with highly complex semiconductors.
• Knowledge of industry standard SOC components (bus fabrics, I/O devices, processors).
• Knowledge of SW architectures and firmware development.

Expected Base Pay Range (USD)

227,000 - 335,890, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.

Additional Compensation and Benefit Elements 

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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