We are looking for a senior Digital Verification contractor to take ownership of verification for complex blocks and subsystems in our SoC, including Efficient's proprietary Fabric technology. You will join our newly formed Verification & Emulation team and work directly with RTL designers and architects. We need someone who can ramp quickly on a spec, stand up or extend a UVM environment with minimal direction, and drive it to coverage closure.

Tasks

• Own verification of assigned blocks and subsystems from spec review through coverage sign-off.
• Write verification plans from design and architecture specifications, and review them with design and architecture leads.
• Architect, build, or extend UVM/SystemVerilog testbenches: agents, scoreboards, reference models, sequences, and constrained-random tests.
• Write SystemVerilog assertions and functional coverage models, and drive functional and code coverage to closure.
• Debug complex simulation failures and work with RTL designers to root-cause and fix bugs.
• Report verification status, risks, and coverage gaps clearly to the DV lead and design team.
• Document your environment so it can be handed off to and maintained by the full-time team.

Required qualifications

• Education: Bachelor's or Master's/PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 8+ years of ASIC/SoC design verification, with multiple projects taken from testbench development through tapeout.
• UVM and SystemVerilog: Expert in UVM testbench architecture and SystemVerilog for verification, including classes, constraints, interfaces, functional coverage, and assertions (SVA).
• Coverage closure: A track record of driving functional and code coverage to sign-off on multi-million-gate designs.
• Debug: Strong ability to debug complex simulation failures independently using industry-standard tools (VCS/Verdi, Xcelium, or Questa).
• Scripting: Python for regression automation, log analysis, and coverage post-processing.
• Independence: Able to ramp quickly on a new design and deliver with minimal supervision.
• Communication: Clear written and verbal communication of status, risks, and tradeoffs to peers and leadership.

Ways to stand out

• C/C++ for reference modeling or SoC-level tests, including DPI integration.
• Formal verification with JasperGold or similar tools.
• Experience building or using agentic AI flows for DV, such as automated regression triage or failure debug.
• Background in computer architecture, dataflow or spatial architectures, or ML accelerators.
• Power-aware verification with UPF.

We offer a competitive hourly rate of $80–$130 per hour on a 1099 contract basis. Final compensation will depend on experience, seniority, and location, with some flexibility for the right candidate.