About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Summary of Role 

GlobalFoundries is seeking a Device Modeling Engineer with a core background in semiconductor device physics to develop, extract, validate, and deploy predictive models from room temperature to cryogenic temperatures. This role will translate measured behavior and device physics into simulation-ready compact models for transistors and models for superconducting and photonic elements, enabling cryoCMOS PDKs, quantum control and readout circuits, photonic design enablement, and differentiated foundry solutions. 

Essential Responsibilities 

Develop and calibrate physics-based compact models for CMOS and related transistor technologies across room-temperature and cryogenic operating regimes, including nominal, corner, and statistical model behavior. 

Develop, calibrate, and validate simulation-ready models for superconducting and photonic elements using measured data, relevant physical mechanisms, and appropriate modeling frameworks. 

Plan and execute parameter-extraction and model-validation workflows using electrical characterization data from device test structures and test chips. 

Correlate model behavior with measured data, semiconductor device physics, relevant superconducting and photonic physics, and TCAD or other physics-based simulation results; identify model limitations and drive corrective actions. 

Define device and test-structure requirements needed to extract, validate, and continuously improve models for cryogenic design enablement. 

Integrate and qualify model files within PDK and EDA simulation environments, including regression testing, convergence checks, documentation, and release readiness. 

Analyze temperature-dependent device behavior, variability, mismatch, noise, and reliability effects and translate findings into practical guidance for circuit designers. 

Collaborate with device engineering, technology development, characterization, PDK, EDA, and circuit-design teams to establish model requirements and delivery priorities. 

Communicate model assumptions, validation results, known limitations, and recommended usage through technical reports, model documentation, and design-team reviews. 

Other Responsibilities 

Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs. 

Work and collaborate on other projects and/or assignments as needed. 

Required Qualifications 

Education - Bachelor's degree in Electrical Engineering, Microelectronics, Physics, Applied Physics, or a related field. 

Experience - Minimum 5 years of experience applying semiconductor device physics to device modeling, transistor compact-model development, parameter extraction, device characterization, or closely related work. Final experience requirements should be aligned with GF scoping guidelines for the approved job level. 

Strong background in semiconductor device physics and demonstrated understanding of transistor compact modeling and MOSFET electrical behavior, including short-channel effects, leakage, capacitance, variability, and temperature dependence. 

Demonstrated capability to develop or apply models for superconducting and photonic elements, including selection of appropriate physical effects, parameterization, validation, and deployment in circuit- or system-level simulation environments. 

Hands-on experience with compact-model parameter extraction and model validation using measured device data. 

Experience with SPICE-class circuit simulation and commercial EDA environments such as Cadence Virtuoso/Spectre, Synopsys PrimeSim/HSPICE, or Siemens EDA tools. 

Proficiency in data analysis and automation using Python, MATLAB, or equivalent scripting/programming tools in a Linux/Unix environment. 

Ability to interpret electrical characterization data and communicate technical conclusions clearly to device, modeling, PDK, and design stakeholders. 

Travel - Up to 10%. 

Fluency in English - written and verbal. 

Preferred Qualifications 

Master's degree or PhD in Electrical Engineering, Microelectronics, Physics, Applied Physics, or a related field. 

Advanced experience developing or calibrating transistor compact models such as BSIM4, BSIM-CMG, PSP, or related model families. 

Experience with cryogenic electronics or semiconductor device behavior from approximately 300 K to 4 K, including freeze-out, threshold-voltage shifts, mobility changes, self-heating, noise, and model convergence challenges. 

Experience with commercial parameter-extraction platforms such as Keysight IC-CAP or Synopsys Mystic, or with internally developed automated extraction frameworks. 

Background in TCAD simulation and correlation among process/device simulation, compact models, and measured silicon. 

Experience with statistical modeling, process-corner generation, local mismatch, Monte Carlo methods, design-of-experiments, or semiconductor variability analysis. 

Experience supporting PDK releases, model QA, regression testing, version control, and customer-facing model documentation. 

Advanced experience modeling superconducting elements, photonic devices, or both, with familiarity in superconducting/quantum hardware interfaces, photonic design enablement, cryoCMOS circuits, quantum control/readout electronics, or RF/analog design requirements. 

Project management skills, including the ability to innovate, execute solutions that matter, and navigate ambiguity. 

Strong written and verbal communication skills and strong planning and organizational skills. 

Expected Salary Range

$98,000.00 - $176,000.00

The exact Salary will be determined based on qualifications, experience and location.