Job Responsibility:  

·       Verification strategy for mixed signal designs and systems

·       Create verification plans and tracability of requirements to ensure they are covered

·       Create functional models of analog blocks using systerm verilog for use in SOC system verification.

·       Create AMS models of analog blocks and sub-systems to verify electrical behavior of mixed signals systems.

·       Run simulations and track coverage of verification plans

·       Ensure high quality tape outs and A0 silicon to production.

Your Profile: 

·       Bachelor's Degree in Electronic Engineering, masters degree is preferred

·       10+yrs of production mixed signal verification

·       System Verilog modeling experience required

·       Assertion, checkers, and similar digital verification experience highly desired

·       Strong communication and teamwork skills are required.

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