À propos de ce poste ESD and Latch-up Test Engineer chez NVIDIA
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
We seek an outstanding ESD and Latch-up Test Engineer who will compose, develop, and carry out qualification tests for ESD and latch-up on GPU and Tegra products. This position is based in Santa Clara, CA, USA, and provides an excellent opportunity to work on advanced semiconductor technologies with a team committed to innovation, reliability, and technical excellence.
What you will be doing:
Plan and perform ESD and Latch-up qualification for new and updated products.
Develop HBM, CDM, Latch Up I-test, and supply overvoltage stress programs in accordance with JEDEC/AEC standards.
Collaborate with external vendors to compose, build, and validate ESD and LU test fixtures, including test boards, test sockets, and thermal plungers.
Conduct ESD and latch-up characterization on test chips incorporating new I/O interfaces and ESD protection structures.
Provide regular test status updates to internal engineering and program teams.
Debug marginal or failing pins, and work closely with Failure Analysis, Design, and Product teams to identify root causes and implement corrective actions.
Maintain, resolve problems in, and calibrate in-house test equipment, including ESD HBM testers, latch-up testers, CDM testers, 2-pin testers, and TLP testers.
Update and maintain internal ESD and latch-up databases, documentation, and online resources.
What we need to see:
Familiarity of JEDEC and AEC standards related to ESD and latch-up qualification.
Practical experience working with MK4 and Orion testers during the development of ESD and Latch-up stress programs.
Solid knowledge of CMOS I/O circuits and ESD protection structures.
Proficiency in analyzing IC electrical test data and interpreting qualification results.
Experience debugging ESD or latch-up failures at the pin, circuit, or product level.
Familiarity with semiconductor reliability qualification flows.
Experience coordinating with external test vendors and internal multi-functional engineering teams.
Strong communication skills with the ability to summarize technical findings clearly and drive issues to closure.
Some experience with 93K tester program development.
5+ years of related experience, with a Bachelor's degree in Electrical Engineering, Physics, or equivalent experience.
Join NVIDIA and contribute to our legacy of innovation while working on ambitious projects that build the future of computing!
Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
