Job Details:

Job Description:

About the Role
You will be working in the Silicon Design Automation (Design Automation / CAD) group as a senior owner of Reliability Verification tools, flows and methodology (TFM), responsible for developing and supporting our RV flows across custom/analog and ASIC design styles — and for running block-level RV yourself on live projects.

Our design teams are our users. You will work directly with design team leads, physical design owners, and the reliability, QRE and technology enablement communities to understand what each project and each process node demands of the RV flows, then define, build, release and support the methodology and tools that gets designers to RV sign-off.

RV development and RV execution are both core to this job, not a side project. You will own the flows, and you will also be one of the engineers who runs block and IP-level EM/IR analysis, triages violations with designers, and drives them to closure against project RV set points and sign-off limits.

You will develop and release production-grade RV flows, regressions and automation, and support the design teams running them: triaging tickets, debugging EM/IR issues alongside designers during live tape-outs, and delivering the user guides, training and labs that make the methodology stick.
Block, IP, subsystem and full-chip RV all live in this domain, spanning custom/analog and cell-based design styles, and touching adjacent reliability checks — PERC, ESD/latch-up, C4 bump Imax, HV-DRC, EOS and aging — as documented in the Altera silicon milestone reliability criteria.

You will represent the RV design automation domain with design leads, physical design, the Global RV team, QRE and technology enablement in cross-functional reliability forums, and you will drive engagements with the major EDA vendors — evaluating capabilities, escalating what blocks us, and shaping roadmaps for RV tools.

Genuine modernization work. We are consolidating construction, verification and analysis flows into a unified flow environment with managed workspaces and released collateral, and enabling new process nodes as they arrive. There is meaningful greenfield work in RV — vectorless and vector-based EM/IR, thermal-aware and self-heat methodology, statistical EM/DPM budgeting, and collateral (LEF / Liberty / CMM) generation and validation — not just incremental maintenance.

Responsibilities

• Own, develop and release RV tools, flows and methodology for custom/analog (totem_rv) and ASIC (R2G RV) design styles, including flow scripts, regressions, automation, dashboards and release notes.
• Execute block and IP-level RV runs (static and dynamic EM/IR, self-heat, peak current) on active projects; triage violations, identify hot spots, and drive fixes to closure with design and layout owners.
• Enable RV for new process nodes and new projects: intercept foundry and technology collateral, update flow configurations and derates, and build regression test cases proving each RV step runs correctly.
• Support project milestone execution: block RV rolling, IP/subsystem RV completion with hot-spot fixes, and full-chip RV continuation through tape-in and sign-off reviews.
• Provide first-line user support for the RV domain: ticket triage, debug alongside designers, user guides, FAQs, cheat sheets, training and labs.
• Drive EDA vendor engagement for RV tools — evaluations, benchmarking, bug escalation, feature requests and roadmap influence.
• Apply AI/ML and modern scripting practice to reduce RV runtime, resource usage and debug effort. 

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$149,100 - 215,925 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

#LI-MD1

Qualifications:

Minimum Qualifications

• Bachelor's degree or Master's degree in Electrical Engineering, Computer Engineering, or related field, with 6+ years of experience in IC design, physical design, or design automation (CAD) — including hands-on Reliability Verification (EM/IR) experience.
• Hands-on production experience with at least one industry-standard EM/IR tool: Ansys Totem, Ansys RedHawk/RedHawk-SC, Cadence Voltus or Voltus-XFi.
• Working understanding of electromigration, static and dynamic IR drop, self-heating, current density and peak-current analysis, and how RV set points translate into design sign-off criteria.
• Practical experience running verification or analysis on real design databases and debugging results with designers.
• Strong programming and automation skills in Python and Tcl, plus shell scripting in a Linux/LSF-style compute environment.
• Ability to work effectively and independently across geographically distributed teams (San Jose, Penang, India), with attention to detail and strong written and verbal communication.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.