Responsibilities

• Define and implement digital micro-architecture for HBM base-die subsystems, including channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers, telemetry, performance monitoring, and reliability features.
• Translate system requirements into timing, power, and area objectives while partnering with physical layer and system architects; develop and maintain interface specifications for bus protocols, clock-domain crossings, and reset architectures.
• Develop, integrate, and debug synthesizable SystemVerilog RTL, including multi-channel logic, interrupt handling, register maps, scan infrastructure, and design-for-test interfaces while supporting integration and ECO activities.
• Work alongside design verification teams to build verification strategies, reach coverage goals, perform CDC/RDC analysis, and resolve RTL, testbench, and gate-level issues.
• Support silicon bring-up and post-silicon validation through debug enablement, root-cause analysis, and partnership with DFT and test engineering teams; leverage AI-Assisted and AI-Enabled tools to improve engineering productivity, debug efficiency, and data-driven analysis.

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with digital design, SoC integration, or semiconductor development through academic projects, internships, research, or industry experience.
• Solid understanding of SystemVerilog RTL development, clock and reset architectures, CDC/RDC methodologies, and low-power design concepts.
• Understanding of design-for-debug and design-for-test principles and the ability to collaborate effectively within multi-functional engineering teams.
• Experience working in AI-Assisted or AI-Enabled environments, or demonstrated willingness to apply AI tools to support engineering workflows, debug activities, and technical analysis.

Preferred Qualifications

• Exposure to post-silicon validation, silicon bring-up, or structured hardware debug methodologies.
• Familiarity with scan, MBIST, LBIST, or related test and debug architectures.
• Experience contributing to verification planning and partnering with design verification teams to achieve functional and code coverage objectives.
• Knowledge of micro-architecture optimization, timing closure concepts, and design tradeoffs related to constraints and path intent.
• Experience Applying AI, Employing AI, or Using AI for data analysis, debug automation, productivity enhancement, or performance optimization within semiconductor design environments.