NVIDIA's most critical silicon features — the circuits that catch failures before they propagate, extend silicon lifetime under the hardest workloads, hold their margins across every voltage and temperature corner, and stay clean in the presence of the noise and transient currents that real silicon at scale generates — these are the circuits that determine whether a product earns long-term trust in the field. They don't validate themselves. They require a team that thinks like circuit designers, works like experimentalists, and moves with the urgency of a production program. This role leads that team.

The Silicon Co-Design Group owns the boundary between design intent and silicon reality. As the manager of the Circuit Co-Design function, you own the people, the methodology, and the outcomes. You are not a coordinator. You are the technical and organizational force that ensures this team closes the hardest problems, ships with confidence, and gets better with every program.

What you'll be doing:

• Lead a team of senior engineers across silicon bring-up, post-silicon validation, and circuit co-design for NVIDIA's safety, reliability, and performance enhancement features — including the noise, dI/dt, and power integrity challenges that determine whether those features hold under real operating conditions across the full PVT space and product lifetime.
• Set technical direction. Define how the team characterizes circuits, closes simulation-to-silicon gaps, quantifies noise and dI/dt margins, analyzes aging and reliability mechanisms, triages failures, and drives fixes to confirmation. Your methodology is what scales across programs and generations.
• Own the hard calls. When a reliability circuit isn't holding its margin, when a dI/dt transient is coupling into a sensitive feature, when substrate or supply noise is the hidden variable behind a failure that looks like something else, when a production program is at risk — you are in the room, and your judgment is what the organization acts on.
• Hire and develop outstanding engineers. Build a team with depth in circuit co-design, power integrity, noise characterization, reliability physics, and post-silicon validation. Make the people around you measurably better.
• Drive cross-functional alignment. Your team sits at the intersection of circuit design, architecture, VLSI, PDN, reliability engineering, firmware, and product. You ensure that intersection produces decisions, not delays.

What we need to see:

• BS or MS in Electrical Engineering, Computer Engineering, or equivalent.
• 10+ overall years in silicon validation, circuit co-design, or post-silicon characterization, with at least 3 years leading technical teams.
• Deep circuit fundamentals — analog, digital, mixed-signal — with genuine expertise in power integrity, noise analysis, dI/dt characterization, and reliability and aging mechanisms. Deep enough to earn the respect of the engineers you lead and challenge the conclusions they bring you.
• Hands-on background with substrate and supply noise analysis, PDN design and mitigation, and silicon reliability mechanisms — the intuition to know when a circuit failure is a circuit problem and when noise, aging, or a power transient is wearing a circuit's clothes.
• A track record of hiring strong engineers, developing them into recognized experts, and retaining them.
• The ability to hold technical depth and organizational breadth simultaneously — never losing the thread on a critical silicon reliability issue while managing a team across multiple programs.

Ways to stand out from the crowd:

• Built or scaled a circuit co-design or reliability characterization organization and can speak to what worked and what didn't.
• Personally closed a production-critical failure where noise, dI/dt, aging, or a power integrity interaction was part of the answer — and driven it all the way through to resolution.
• Driven adoption of AI-driven flows across a validation or co-design team and set the guardrails that made it safe to do so.