Job Details:

Job Description:

Join our high‑performance Silicon Validation team and play a critical role in enabling robust FPGA security for next‑generation FPGA and SoC devices. You will lead device‑level and IP‑level validation of FPGA, secure boot and root‑of‑trust features to ensure industry‑leading security, reliability, and system integrity.

This role offers hands‑on exposure to secure FPGA architectures, SoC bring‑up and system‑level debug, while collaborating closely with architecture, design, firmware, and platform teams to influence future secure FPGA products.

Key Responsibilities

• Develop comprehensive validation strategies for FPGA, security, aligned with device architecture, security requirements, and business objectives.
• Perform security feature validation, including secure boot, authentication, encryption, key management, root‑of‑trust, and protection against misconfiguration or unauthorized access.
• Create and execute test cases and vectors for configuration robustness, security corner cases, fault injection, and negative testing scenarios.
• Perform device and system bring‑up, debugging, security violations, boot hangs, issues across silicon revisions.
• Work with evaluation boards, reference platforms, and customer‑like systems to ensure interoperability and real‑world usage coverage.
• Drive innovation in validation methodologies, automation, and infrastructure, improving test coverage, scalability, and efficiency for future FPGA and SoC generations.
• Collaborate with hardware, firmware, and board design teams on security‑ready evaluation platforms, influencing observability and debug capability.

Qualifications:

• Bachelor’s or Master’s degree in Electrical & Electronics Engineering, Computer Engineering, or related field.
• 8+ years of hands‑on silicon validation experience, with strong focus on FPGA configuration, security, SoC, or embedded processor subsystems.
• Strong knowledge of hardware security concepts, such as secure boot, authentication, encryption, key storage, lifecycle states, and threat modeling.
• Hands‑on experience with system‑level validation and debug, including power‑on bring‑up, failure analysis, and silicon issue triage.
• Familiarity with FPGA and SoC architectures (strong advantage).
• Experience or familiarity with Python for automation, scripting, and test infrastructure; Verilog familiarity is a plus.

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