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Job Description:

The candidate will be responsible for leading and executing Synthesis, Static Timing Analysis (STA), Formal Verification, and low-power implementation activities of Mixed Signal (MXS) blocks. Additionally, this role acts as the IP Release Owner, managing the critical integrity checks prior to IP block handoff to consumers. You will utilize advanced automation and modern engineering workflows to drive functional, physical, and deployment readiness for complex ASIC blocks in advanced technology nodes.

Responsibilities Include:

• Synthesis & Low-Power Implementation: Execute synthesis and run static checks (CDC, RDC, UPF/CPF power intent) for digital/mixed-signal blocks.
• Timing & Constraint Management: Create, validate, and maintain timing constraints. Perform STA and define timing signoff methodologies, including corners and derating.
• Formal Verification: Run Formal Verification and logical equivalence checking (LEC) throughout the design flow to guarantee functional correctness.
• Timing Closure: Generate and implement timing/functional ECOs to drive timing closure, evaluating pre- and post-route Quality of Results (QoR).
• IP Release Ownership: Serve as the final gatekeeper for IP deployment by driving the release validation flow, auditing files for synchronization gaps, and ensuring proper tagging via revision control utilities before handing off to customers or SoC teams.
• Workflow Automation: Build and deploy custom script-based automation to streamline implementation and audit tasks.

Qualifications:

• Extensive experience with high-complexity silicon in advanced technology nodes.
• Expertise in industry-standard tools for synthesis, STA, formal verification, and low-power audits (e.g., Design Compiler, Genus, PrimeTime, Tempus, Formality, VCLP).
• Hands-on experience with hardware data management tools (e.g., Git, DesignSync or equivalent) for managing complex, hierarchical IP releases.
• Strong familiarity with UPF/CPF low-power design methodologies.
• Automation & Modern Tooling: Experience developing custom automation tools using scripting languages (Tcl, Perl/Python) to optimize daily workloads, alongside experience leveraging AI code-assist tools to accelerate script generation/code debug.
• Strong analytical mindset, excellent problem-solving skills, and acute attention to detail.
• Effective communication skills to act as a cross-functional liaison between global design and physical implementation teams.
• Direct experience with physical design implementation steps, including partitioning, floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (LVS/DRC using tools like Calibre, ICC2, or Innovus) is a plus.
• Direct or indirect experience with RTL design and architecture is a plus.
• Contributed to the successful tapeout or release deployment of at least 1–2 high-complexity ASICs/SoCs.

Education and Experience Required:

• BS in Electrical Engineering, Computer Engineering, or a related field with 8+ years of related experience, OR an MS with 6+ years of related experience.

Compensation and Benefits

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

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