About the role

Anthropic is building custom silicon for Claude. The hardware our models run on is one of the most direct levers we have on capability, cost, and reliability — and we've decided to take design authority over it ourselves.

We're looking for a Technical Program Manager to own end-to-end execution of our silicon, from architecture definition through tapeout, first-silicon bring-up, and production ramp. You'll be working alongside a small group of domain experts across front-end design, verification, physical design, DFT, analog/mixed-signal, foundry, and packaging. There is no process to inherit — you'll build the execution machinery this program runs on.

This is a partner-heavy program by design. You'll drive a portfolio of external engagements — ASIC design services, IP vendors, foundry, and OSAT. You should have shipped chips before, know what a realistic silicon schedule looks like and its failure modes, and be comfortable making consequential program calls without a large organization behind you. And because this is Anthropic, you'll have Claude as a collaborator — we expect the TPMs on this team to push hard on what AI-assisted program management can look like.

Key responsibilities

• Own the integrated silicon program plan — architecture closure, RTL freeze, DV milestones, IP delivery, PD closure, DFT, tapeout, and post-silicon bring-up.
• Drive external partner execution across ASIC design partners, IP vendors, foundry, and packaging/test.
• Run technology and IP selection as a program: track candidate vendors and options, drive evaluations to a decision, and land the build / buy / license calls with engineering leadership.
• Build the execution mechanisms a silicon team needs — milestone definitions, risk and dependency tracking, design reviews, release management, exec reporting — and keep them lightweight enough that engineers actually use them.
• Manage the interface between silicon and its consumers: hardware systems for package/board/bring-up, and inference/kernels/compiler teams for hardware-software co-design, so trade-offs land as coordinated decisions rather than late surprises.
• Own the post-silicon program — bring-up planning, ATE/test handoff, sample distribution, validation, and the path to production readiness.
• Develop and share AI-assisted approaches to program management — schedule and dependency modeling, spec and milestone consistency checking, partner-deliverable tracking, status synthesis.

Minimum qualifications

• 8+ years in silicon/SoC program management, chip lead, or an equivalent role that owned a chip schedule end to end.
• Direct ownership of at least one program that taped out and reached production, with milestones you can speak to in detail — including where it slipped and what you did about it.
• Working technical fluency across the silicon lifecycle — front-end, DV, PD, DFT, foundry, packaging.
• Experience running external silicon partners — ASIC houses, IP vendors, foundry, or OSAT — including SOW scoping, delivery tracking, and escalation.
• Track record of building program mechanisms from scratch on an ambiguous, fast-moving effort.
• Strong written communication — plans, reviews, and exec updates that many teams depend on.
• Comfort operating with high autonomy and limited process on a highly dynamic program.

Preferred qualifications

• Experience on ML accelerators, high-performance compute, networking, or other large, high-bandwidth SoCs at advanced process nodes.
• Experience on a first-generation or early silicon program, including standing up flows, methodology, or vendor relationships from nothing.
• Experience with both partner-executed and fully in-house programs, and a view on the trade-offs between them.
• Prior hands-on engineering background in one or more silicon domains (design, DV, PD, DFT, or SI/PI).
• Familiarity with the chip-package-system interface and co-design with a hardware systems team.
• Experience with hardware-software co-design programs — working directly with compiler, kernel, or runtime teams.
• Practical experience using AI tools in your own workflow, and clear ideas about where they help and where they don't.
• BS/MS in EE, CE, CS, or a related field, or equivalent experience.