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Über diese Sr Principal Engineer -SIPI Stelle bei Cadence Design Systems

Cadence Design Systems · Vor Ort · SAN JOSE

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Sr Principal Enginee
This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems. We are looking for a Sr Principal SI/PI Engineer who will be a key contributor to our advanced high speed IP products. This is a hands-on technical position.
Main Job Tasks and Responsibilities:
• Work on test chip package design SI/PI optimization and verification.
• Work on evaluation board design optimization for best SI/PI performance.
• Provide extracted and measured channel models for chip designers in the R&D team.
• Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries.
• Review customer package and board designs and simulation results. Help with providing feedback to customers to ensure best possible performance of our IP in their ASIC.
• Work on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models.
• Help with SI/PI related debug of test chips or customer ASICs in the lab.
Position Requirements:
• M.S. or Ph.D. Electrical Engineering (or similar degree)
• 3+ years of experience preferably working with high speed SerDes and PHYs
• Good understanding of high speed SerDes architecture
• Hands on lab experience with instruments like high speed oscilloscopes, TDRs, VNAs, spectrum analyzers, etc.
• Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave
• Experience with IBIS-AMI model simulations
• Experience with simulation result to lab measurement correlation
• Good understanding of PCB and FCBGA design rules and requirements
• Strong debugging and problem-solving skills
• Excellent communication and presentation skills to effectively communicate with both customers and internal stake holders

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

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Wie sich dieses Gehalt für Principal Engineer vergleicht

Diese Stelle zahlt $220,000/yr — im Einklang mit der üblichen Spanne für Principal Engineer Stellen.

$174,400 dem Median $220,000 $305,320

Übliche Spanne $201,250–$270,044/yr, aus 146 vergleichbaren Principal Engineer Anzeigen auf JobsRadar (Vergütung auf USD hochgerechnet). Gehaltseinblicke für Principal Engineer ansehen →

Über Cadence Design Systems

Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [email protected] . Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64

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