JOB DESCRIPTION:

The Principal Test Engineer serves as the technical resource and acts as Test Engineer of BG MOS (ssMOS) at local site, supporting new product introduction (NPI) and package transfers. This role ensures test programs, and methods are optimized and aligned within test specifications, drives test yield improvements, supports NPI/ production ramp-ups.

RESPONSIBILITIES:

• Responsible for BG MOS R34 Testing for New Product Introduction / New package development in ATSN assembly site.
• Highly preferred to be experienced in working with ITEC Test Equipment such as Parsets and knowledgeable in interfacing ITEC Test Equipment with other measurement instruments (Ruggedness, Rg). 
• Will drives strategy for Test equipment and Test methodology in ATSN for BG MOS (ssMOS products).
• Provide technical expertise in MOSFET testing in the Malaysian Assembly Site.
• Will ensure BG MOS R34 final test capability and best practices are deployed and maintained in ATSN.
• Will identify, root cause and resolve tester line bottleneck for both NPIs and Industrial Transfer in ATSN.
• Will help identify requirements for Safe Launch to ensure smooth volume ramp-up in ATSN.
• Enhance and Improve testing to protect Final Test Yield and apply dynamic algorithms for outliers’ analysis.
• Increases BE line capacity and where necessary performs advanced product measurements to support customer inquiries or complaints.
• Carries out other tasks as defined by R34 R&D Test Development.

QUALIFICATIONS:

• Bachelor’s degree in engineering (Electronics, Electrical, Mechanical) or any related Engineering discipline.
• Strong understanding of semiconductor product test methodologies, test equipment, and manufacturing test processes.
• At least 20+ years of relevant experience in a semiconductor manufacturing environment, with expertise in Final Test Operations, Test Equipment, Test Process, or Test Engineering.
• Microsoft Office skills (Excel, PowerPoint, and Word).
• Willing to travel.
• Hands-on experience with Automated Test Equipment (ATE) and semiconductor test handlers.  Experienced with ITEC Test equipment (Pup, uParset or nParsets). MOSFET and Discrete semiconductor verification and testing.
• Familiar with UIS (Unclamped Inductive Switching) testing and LCR testing and interfacing the ATE with UIS and Rg testing.
• Background in supporting R&D/NPI for MOSFET devices, new packages and devices, which may include creation/ revision of test jobs to enhance testing and protecting Final Test Yield.
• Background in setting up/ qualification Tester/ Test handler/ Test contacts/ New Test Equipment.
• Familiar with data analysis tools/ statistical tools (Exensio, Spotfire, Power BI, JMP, Statistica, etc).
• Background in Test Yield analysis and improvement.
• Knowledge in hardware development.
• Onsite Expertise and representative for BG MOS.
• On time test job deployment.
• Test yield on target as per released devices.
• Test qualification reports.

Talent acquisition based on Nexperia vacancies is not appreciated. Nexperia job adverts are Nexperia copyright © material and the word Nexperia® is a registered trademark.

D&I Statement

As an equal-opportunity employer, Nexperia values diversity not just because it is the right thing to do but because diverse teams perform better. We are dedicated to being inclusive, and a proof point of this dedication is that we were the main partner of the very first Dutch Paralympic Team NL House during the Paris 2024 Paralympic Games. Our recruitment process is inclusive and accessible to all, and we consider all applicants fairly, as well as providing a safe work environment and reasonable adjustments where requested.

In addition, we offer our colleagues the possibility to join employee resource groups such as the Pride Network Group or global and local Women's groups. Nexperia is committed to increasing women in management positions to 30% by 2030.