The PMTS Digital Design Engineer will lead the architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystem components. This role requires deep expertise in processor design, strong technical leadership, and the ability to drive complex SoC development programs from concept through silicon bring-up.

The candidate will work closely with architecture, verification, physical design, DFT, firmware, and software teams to deliver competitive processor products meeting performance, power, area, and schedule targets.

Essential Responsibilities:

Processor Microarchitecture & RTL Design

• Develop and implement microarchitecture for CPU cores, cache subsystems, memory management units (MMU), interconnects, and system controllers.
• Translate architectural specifications into high-quality RTL designs using Verilog/SystemVerilog.
• Define and review detailed design specifications, block-level architectures, and implementation strategies.
• Drive performance optimization, power reduction, and area-efficient design methodologies.
• Analyze and resolve complex design trade-offs involving latency, throughput, and scalability.

Technical Leadership

• Lead critical processor design initiatives across multiple functional blocks.
• Mentor junior and senior engineers on microarchitecture, RTL coding practices, and design methodologies.
• Conduct architecture, microarchitecture, and RTL design reviews.
• Establish design guidelines and best practices across the organization.
• Influence roadmap and technology decisions for future processor generations.

Cross-Functional Collaboration

• Partner with architects to evaluate new features and enhancements.
• Work closely with verification teams to define verification plans and close coverage.
• Support synthesis, timing closure, low-power implementation, and physical design activities.
• Collaborate with DFT teams to ensure manufacturability and testability.
• Support silicon bring-up, debug, characterization, and production ramp activities.

Performance Analysis & Optimization

• Conduct design performance analysis and bottleneck identification.
• Drive microarchitectural enhancements to improve IPC, memory latency, and system efficiency.
• Analyze workload behavior and benchmark performance.
• Participate in power-performance-area (PPA) optimization efforts.

Required Qualifications:

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
• 12+ years of experience in processor, CPU, DSP, or complex SoC digital design.
• Deep understanding of processor microarchitecture, including:
  • Pipeline design
  • Cache architectures
  • Branch prediction
  • Memory hierarchy
  • MMU/TLB designs
  • Interrupt and exception handling
  • Coherency protocols
• Expert-level RTL design experience using Verilog/SystemVerilog.
• Strong understanding of synthesis, timing analysis, CDC, RDC, and low-power design techniques.
• Experience with industry-standard EDA tools and design flows.
• Strong debugging and problem-solving skills.

Preferred Qualifications

• Experience with RISC-V, ARM, MIPS, ARC, or custom CPU architectures.
• Knowledge of multi-core and heterogeneous computing systems.
• Experience in AI/ML acceleration, vector processing, or advanced computing architectures.
• Experience with performance modeling and architectural simulation.
• Silicon bring-up and post-silicon debug experience.
• Exposure to safety-critical designs (ISO 26262, DO-254) is a plus.