In this role, you will be working on leading-edge packaging technologies to enable AI architectures that set new industry standards for compute power, performance, and efficiency. As a member of the Packaging team, you will collaborate with several teams to identify key failure modes under product use conditions and run appropriate parametric design studies to influence product and package design upstream. You will be responsible for the package stack-up analysis, co-optimizing mechanical, optical and thermal aspects that influence package form factors, and driving socket/enabling mechanisms. You will utilize Geometric Dimensioning and Tolerancing (GD&T) to propose solutions that finalize the design. Your work will result in advanced package designs that meet power dissipation, assembly, optical, and reliability requirements, while delivering a system level solution for leading edge products in the data centers and high-end compute segment.

Responsibilities:

• Create CAD models of package stack-up and associated components.
• Perform mechanical design analysis to identify and implement solutions that improve package mechanical integrity.
• Execute tolerance stack-up analyses and create GD&T drawings for advanced packages — including optically aligned assemblies where micron-level precision defines product performance
• Apply manufacturing expertise to influence design choices, perform FMEAs, and evaluate the cost implications of process and design decisions.
• Collaborate with package and systems teams to ensure packaging solutions comply with system boundary conditions.

Requirements: 

• BS or MS in Mechanical Engineering or a related field.
• Minimum of 3 years of mechanical design experience in semiconductor packaging, optoelectronics, or photonics modules.
• Proficiency in CAD tools such as Solidworks or Creo, with a focus on mechanical design best practices.
• Expertise in Geometric Dimensioning and Tolerancing (GD&T) and tolerance stack-up analysis.
• Manage prototype builds with external vendors, validating the designs, and ensuring the scalability to high volume manufacturability.
• Working knowledge of semiconductor packaging technologies, including the mechanical and thermal trade-offs of 3D, 2.5D, and FCBGA architectures.

Preferred Qualifications

• Knowledge of ASME Y14.5 standards.
• Ability to drive results independently and with minimal supervision.
• Working knowledge of FEA tools (ANSYS, Abaqus, or similar) for structural and thermal analysis.
• Fiber array unit (FAU) attach, optical connector, or photonic alignment experience.
• Experience with liquid cooling or advanced thermal architectures for AI/HPC systems.
• Exposure to high-volume manufacturing and OSAT engagement in Asia.
• Strong cross-functional communication skills and a bias toward fast, data-driven iteration.