Job Details:

Job Description:

Job Summary

Altera is seeking a Senior FPGA Soft IP Design Engineer to architect, develop, and productize FPGA Soft IP cores released through Quartus and Platform Designer.

You will own parameterizable RTL from micro-architecture through packaging, verification, and customer-ready delivery — producing reusable, high-performance IP that customers instantiate in production designs.

This role is for an experienced individual contributor who can take an IP from specification to Quartus catalog release, make sound PPA and interface trade-offs, and guide junior engineers. Hands-on experience with high-speed interface IP such as JESD204B/C or Ethernet is a strong plus.

Job Responsibilities

• Architect, design, and implement FPGA Soft IP cores in VHDL, Verilog, or System Verilog, targeting high performance, low resource usage, and timing closure across Altera device families.
• Develop parameterizable, reusable IP with clean configuration spaces, documented interfaces, and stable upgrade behavior across Quartus releases.
• Own the Soft IP lifecycle: RTL design, synthesis, functional simulation, lint, clock-domain crossing (CDC) analysis, static timing analysis (STA), and example-design bring-up.
• Package IP for Quartus / Platform Designer (Qsys), including metadata, HDL generation, parameter validation, and integration with Native PHY, transceiver, and interconnect IP.
• Define and implement register maps, CSR/AXI-Lite or Avalon-MM control interfaces, reset and clocking schemes, and user-facing data interfaces (AXI-Stream, Avalon-ST, or equivalent).
• Design and maintain simulation testbenches, directed and constrained-random tests, assertions, and regression suites that prove protocol compliance and configuration coverage.
• Collaborate with verification, firmware, software, and hardware teams on memory maps, configuration sequences, example designs, and hardware validation on FPGA development kits.
• Debug IP issues across simulation, synthesis, place-and-route, and hardware; drive root-cause analysis and timely customer or release fixes.
• Author and review design specifications, user guides, release notes, and API/register documentation for internal teams and external customers.
• Lead technical reviews, enforce coding and quality standards, and mentor junior Soft IP designers.
• Support customer inquiries, FAEs, and design-in issues related to Soft IP behavior, integration, and performance.
• Contribute to development-flow and quality improvements (lint/CDC/STA methodology, automation, IP upgrade robustness).

Qualifications:

Job Qualifications

Minimum qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, or a related field.
• Bachelor’s + 6 years, or Master’s + 4 years, of FPGA/ASIC RTL or Soft IP design.
• Strong proficiency in parameterizable RTL using Verilog, SystemVerilog, and/or VHDL.
• Proven experience taking IP through synthesis, simulation, timing constraints (SDC), CDC, and STA.
• Working knowledge of FPGA architecture, fabric resources, clocking, and the Quartus (or equivalent vendor) design flow.
• Experience packaging or integrating IP in Platform Designer / Qsys, Vivado IP Integrator, or a similar IP catalog flow.
• Familiarity with on-chip interconnect and control protocols (AXI4 / AXI-Stream, Avalon-MM / Avalon-ST, CSR/register interfaces).
• Experience with scripting for IP generation, regression, and design automation (Python, Tcl, and/or Perl).
• Proficiency with version control (Git) and structured code review.
• Strong debug, problem-solving, and written/verbal communication skills; able to work independently and lead technical discussions across sites.

Preferred qualifications

• Hands-on design or integration experience with high-speed interface Soft IP — JESD204B/C and/or Ethernet (MAC/PCS, TSE, or related) is a plus.
• 8+ years with clear ownership of a production Soft IP (parameterization, packaging, release).
• Experience with other high-speed or memory interfaces (PCIe, CPRI, Interlaken, DDR) or with Soft IP that sits next to transceiver / Native PHY IP.
• Knowledge of protocol features such as deterministic latency, multi-lane alignment, FEC, or dynamic reconfiguration.
• Exposure to SystemVerilog assertions, functional coverage, and coverage-driven verification (UVM experience is welcome but not required).
• Familiarity with industry EDA tools (simulators, lint/CDC, synthesis) and hardware validation on FPGA development kits.
• Prior experience supporting Quartus IP catalog releases, example designs, or customer-facing IP documentation.
• Demonstrated technical leadership: mentoring, design reviews, and influencing architecture or methodology without formal people management.

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