Tenstorrent is seeking  a highly skilled Physical Design Engineer to drive the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII. This role demands deep expertise in full physical design flow with a specific focus on closing high-speed D2D interfaces for multi-die/chiplet architectures.

This role is remote role open to any location in the U.S.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts.
• Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off.
• Deeply familiar with high-speed interfaces (D2D, PCIe, HBM, SerDes) and the physical challenges that come with them (timing, signal integrity, power integrity).
• Detail-oriented and methodical with STA, constraints, and closure for complex, high-speed designs.
• A hands-on problem solver who enjoys collaborating across analog, digital, and full-chip teams to debug tough issues.

What We Need

• Lead Die-to-Die (D2D) physical implementation and closure, taking high-speed D2D PHYs/controllers from netlist to tapeout.
• Own the full PD flow (RTL-to-GDSII): synthesis, floorplanning, P&R, CTS, optimization, and sign-off.
• Drive timing and verification, including full STA (setup/hold), SI analysis (crosstalk, IR drop), and achieving sign-off quality DRC/LVS.
• Improve and maintain physical design methodologies, flows, and automation scripts (Tcl, Python), with specific focus on D2D routing, power grid design, and timing closure.
• Partner closely with full-chip/chiplet teams to meet all tapeout requirements and with the analog design team to resolve interface issues (LEF/LIB, constraints, integration/debug).
• Apply strong EDA tool expertise across Synopsys/Cadence/Mentor for implementation, analysis, and verification.
• Bring a solid academic foundation: B.S./M.S. in EE/CE or related field.

What You’ll Learn

• How to implement and close cutting-edge D2D interfaces in advanced multi-die/chiplet architectures.
• Advanced strategies for co-optimizing routing, power grid, and timing for high-speed links across dies.
• Deeper integration techniques working with analog PHY teams, including model handoff (LEF/LIB) and constraint-driven interface design.
• How to drive repeatable, scalable PD methodologies for high-speed interfaces that can be leveraged across future chiplets and products.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

Tenstorrent is seeking an experienced EDA/PDK CAD Engineer to build and maintain world-class design infrastructure that accelerates our silicon innovation. In this role, you'll install and optimize PDKs, manage EDA tool flows, and partner with analog, digital, and software teams to continuously improve design efficiency. If you're passionate about solving complex CAD challenges and enabling cutting-edge chip design, we want you on our team.

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A self-driven problem solver with deep knowledge of PDKs, EDA tools, and IC design flows.
• Experienced in troubleshooting complex CAD issues and developing creative work-around solutions.
• Collaborative communicator who actively seeks feedback to improve team productivity.
• Passionate about challenging industry-leading tools and methodologies to drive continuous improvement.

What We Need

• BS, MS, or Ph.D. in Electrical Engineering and/or Computer Science with 5+ years of industry experience.
• Hands-on expertise installing, configuring, and maintaining PDKs and EDA environments.
• Strong background supporting physical verification flows (DRC, LVS, EM/IR, extraction) and mixed-signal simulation.
• Proven ability to work with vendors, foundries, and cross-functional teams to resolve technical issues.

What You Will Learn

• How to architect and scale design infrastructure for state-of-the-art AI silicon development.
• Advanced techniques for optimizing EDA flows across analog, digital, and mixed-signal domains.
• Direct collaboration with world-class engineers to shape tools and methodologies that define industry standards.
• Best practices for proactive CAD support and continuous flow improvement in a fast-paced innovation environment.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

The Mixed Signal IC Layout Design Engineer role involves full-custom physical layout of analog and mixed-signal integrated circuits, turning schematics into manufacturable layouts that meet performance, power, area, and reliability targets in advanced FinFET processes. The role focuses on high quality, high-speed analog/mixed-signal blocks and their integration into larger SoCs.

This role is remote, based out of anywhere in the United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who you are

• An experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os).
• Proficient with Synopsys Custom Compiler or Cadence Virtuoso for custom layout, and Synopsys ICV or Siemens Calibre for physical verification (DRC, LVS, ERC, DFM, Antenna).
• Deep experience in CMOS/FinFET nodes (ideally TSMC or Samsung 12nm–2nm) with delivered silicon and a strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts.
• Detail-oriented and organized, able to own complex blocks independently and collaborate effectively with circuit designers; typically hold a BSEE (or equivalent experience) with ~10+ years in analog/mixed-signal layout.

What we need

• Execute full-custom analog/mixed-signal layout for key blocks (PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, high-speed I/Os) from schematics to manufacturable layouts.
• Develop optimized block and top-level floorplans, placement, and routing that balance area, parasitics, matching, congestion, and integration into our D2D PHY.
• Apply best-known layout practices and optimize parasitics (R/C), coupling, IR drop, and electromigration to meet precision, noise, timing, and power goals while closing DRC, LVS, ERC, DFM, and Antenna.
• Support post-layout extraction and simulation and, as a bonus, contribute layout methodology and automation/scripts (Python, Tcl, SKILL, etc.) to improve team-wide quality and productivity.

What you will learn

• Deep, hands-on experience with cutting-edge FinFET technologies (down to 2nm) and the nuances of mixed-signal layout at these nodes.
• How to integrate high-speed analog/mixed-signal IP into a complex D2D PHY, including interactions across digital, analog, and I/O domains.
• Advanced approaches for managing EM/IR, ESD, latch-up, and physical-verification closure in dense mixed-signal environments.
• How to influence and evolve layout flows, methodologies, and automation, shaping how the broader team delivers high-quality silicon.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.