SR. ASIC DESIGN VERIFICATION ENGINEER (STARSHIELD)

Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Verification Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

RESPONSIBILITIES:

• Responsible for digital ASIC verification at block and system level
• Lead and execute verification test plan, development, and milestones from beginning to end, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs
• Contribute to pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements
• Ability to work in a dynamic environment with changing needs and requirements
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoy being challenged and learning new skills

ADDITIONAL REQUIREMENTS: 

• Ability to work long hours and weekends as necessary to support critical milestones 
• Willingness to travel for off-site testing
• An active clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing

COMPENSATION AND BENEFITS:    
    
Pay range:    
Sr. ASIC Design Verification Engineer: $160,000.00 - $225,000.00/per year    
    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $15,000 annually, once officially briefed into a classified program.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

SR. ASIC DESIGN ENGINEER (STARSHIELD)

Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

RESPONSIBILITIES:

• Design digital ASICs and/or FPGAs for Starshield projects.
• Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
• Work closely with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of experience in RTL implementation and/or FPGA/ASIC development.

PREFERRED SKILLS AND EXPERIENCE:

• Experience solving problems including clock domain crossings and power optimization.
• Experience developing complex ASICs.
• Experience with multicore CPU subsystem design.
• Experience with standard bus protocols (e.g. AXI, AHB, etc.).
• Experience with embedded processors.
• Experience with high speed and low power design techniques.
• Scripting skills (Python, TCL etc.).
• Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
• Ability to work in a dynamic environment with changing needs and requirements.
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
• Enjoy being challenged and learning new skills.

ADDITIONAL REQUIREMENTS: 

• Ability to work long hours and weekends as necessary to support critical milestones.
• Willingness to travel for off-site testing.
• An active TS-SCI clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing.

COMPENSATION AND BENEFITS:    
    
Pay range:    
Sr. ASIC Design Engineer: $160,000.00 - $225,000.00/per year    
    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $15,000 annually, once officially briefed into a classified program.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

PRINCIPAL ASIC DESIGN VERIFICATION ENGINEER (STARSHIELD)

Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Verification Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

RESPONSIBILITIES:

• Responsible for digital ASIC verification at block and system level
• Lead and execute verification test plan, development, and milestones from beginning to end, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs
• Contribute to pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 8+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements
• Ability to work in a dynamic environment with changing needs and requirements
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoy being challenged and learning new skills

ADDITIONAL REQUIREMENTS: 

• Ability to work long hours and weekends as necessary to support critical milestones 
• Willingness to travel for off-site testing
• An active clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing

COMPENSATION AND BENEFITS:    
    
Pay range:    
Principal ASIC Design Verification Engineer: $200,000.00 - $285,000.00/per year    
    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $15,000 annually, once officially briefed into a classified program.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD)

Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

RESPONSIBILITIES:

• Design digital ASICs and/or FPGAs for Starshield projects.
• Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
• Work closely with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 8+ years of experience in RTL implementation and/or FPGA/ASIC development.

PREFERRED SKILLS AND EXPERIENCE:

• Experience solving problems including clock domain crossings and power optimization.
• Experience developing complex ASICs.
• Experience with multicore CPU subsystem design.
• Experience with standard bus protocols (e.g. AXI, AHB, etc.).
• Experience with embedded processors.
• Experience with high speed and low power design techniques.
• Scripting skills (Python, TCL etc.).
• Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
• Ability to work in a dynamic environment with changing needs and requirements.
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
• Enjoy being challenged and learning new skills.

ADDITIONAL REQUIREMENTS: 

• Ability to work long hours and weekends as necessary to support critical milestones.
• Willingness to travel for off-site testing.
• An active TS-SCI clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing.

COMPENSATION AND BENEFITS:    

Pay range:    
Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $15,000 annually, once officially briefed into a classified program.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

FALL 2026 GRADUATE ENGINEER

As a Graduate Engineer, you will be responsible for working on creative solutions to real aerospace challenges. You will be given as much responsibility as our full-time engineers and will be an integral part of the team. If you’ve demonstrated a commitment to academic success and motivation to apply your knowledge outside of the classroom, you are a great candidate!

Graduate Engineer roles are available with a variety of engineering teams across the company including design, manufacturing and operations at Bastrop, TX; Cape Canaveral, FL; Hawthorne (Los Angeles), CA; Irvine, CA; McGregor (Waco), TX; Redmond, WA; Starbase, TX and Vandenberg, CA.

BASIC QUALIFICATIONS:

• 6+ months of applied engineering experience (internship, laboratory, and personal/team project experience is applicable)
• Enrolled in a graduate program by the start of employment and holds a bachelor’s degree in engineering, physics or math discipline
• Applicant for this graduate engineer position must be a (i) U.S. citizen or national, (ii) U.S. lawful permanent resident (e.g., green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158.

PREFERRED SKILLS AND EXPERIENCE:

• GPA of 3.5 or above
• 9+ months experience of application of technical skills outside of the classroom (examples: laboratory, research, extracurricular project teams, volunteering, personal projects or prior internship/work experience)
• Ability to work well in an integrated collaborative team environment, including frequent interactions with technicians, other engineers, and managers
• Ability to work effectively in a dynamic professional setting with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Able to work full time, onsite for a minimum of 12 consecutive weeks beginning in August or September 2026
• Able to provide own transportation for positions at Bastrop, Cape Canaveral, McGregor and Vandenberg locations

COMPENSATION AND BENEFITS:

Pay range:   

Graduate Engineer/Completed Bachelor's: $83,200.00/per year
Graduate Engineer/Completed Master's: $91,000.00/per year
Graduate Engineer/Completed PhD: $100,100.00/per year

Your salary will be determined by academic level. Pay is just one part of your total rewards package at SpaceX. You may also be eligible for a stipend to subsidize relocation costs, as well as access to our comprehensive medical coverage and a 401(k) retirement plan. Students joining SpaceX through our graduate engineer program will receive the opportunity to attend presentations from company leaders, social and networking events, as well as professional and personal development trainings. Graduate Engineers are also eligible for paid company holidays. SpaceX offers 10 or more paid holidays per year.

PROGRAM DESCRIPTIONS:

DRAGON: Dragon is the most advanced human-rated spacecraft in the world. This capsule currently delivers critical science, cargo and crew safely to and from International Space Station, but further iterations and new designs will likely be necessary to extend humankind's reach to the moon, Mars, and beyond. This program includes roles in: Analysis, Avionics, Build Engineering, Integration & Test Engineering, Life Support Systems, Manufacturing Engineering, Materials Engineering, Propulsion Engineering, Structures Design & Engineering, Supply Chain Engineering and more.

FALCON: The Falcon program tackles space exploration’s toughest problems through the ongoing development of our reusable launch vehicles, Falcon 9 and Falcon Heavy. These vehicles are currently responsible for delivering commercial, national security, and NASA satellites into orbit, as well as supply critical science, supplies, and crew to the International Space Station. This program includes roles in: Analysis, Avionics, Build Engineering, Components Engineering, Integration & Test Engineering, Launch Site Operations & Engineering, Manufacturing Engineering, Materials Engineering, Propulsion Engineering, Recovery Engineering, Structures Design & Engineering, Supply Chain Engineering and more.

STARLINK: At SpaceX, we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to 1M+ users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. This program includes roles in: Analysis, Avionics, Components Engineering, Industrial Engineering, Integration & Test Engineering, Manufacturing Engineering, Materials Engineering, Operations Engineering, Structures Design & Engineering, Supply Chain Engineering and more.

STARSHIELD - Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an intern on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. This program includes roles in: Avionics, Build Engineering, Components Engineering, Integration & Test Engineering, Manufacturing Engineering, Materials Engineering, Mechanical Design & Engineering, Structures Engineering, and more.

STARSHIP: The Starship spacecraft and Super Heavy rocket – collectively referred to as Starship – represent a fully reusable transportation system designed to carry both crew and cargo to Earth orbit, the Moon, Mars and beyond. As the most powerful launch system ever developed, Starship will be able to carry up to 100 people on long-duration, interplanetary flights. Starship will also enable satellite delivery, the development of a Moon base and point-to-point transport here on Earth. This program includes roles in: Analysis, Avionics, Automation & Controls, Build Engineering, Civil Engineering, Components Engineering, Industrial Engineering, Launch Site Operations & Engineering, Manufacturing Engineering, Materials Engineering, Propulsion Engineering, Structures Design & Engineering, Supply Chain Engineering, Test Engineering and more.

PHYSICAL DESIGN ENGINEER II (SILICON ENGINEERING)

RESPONSIBILITIES:

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

PREFERRED SKILLS AND EXPERIENCE:

• Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub-micron FinFET and CMOS solid state physics
• Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical project milestones

PHYSICAL DESIGN ENGINEER II (SILICON ENGINEERING)

RESPONSIBILITIES:

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

PREFERRED SKILLS AND EXPERIENCE:

• Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub-micron FinFET and CMOS solid state physics
• Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical project milestones

COMPENSATION AND BENEFITS:

Pay range:    
Physical Design Engineer/Level II: $145,000.00 - $175,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

PHYSICAL DESIGN ENGINEER II (SILICON ENGINEERING)

RESPONSIBILITIES:

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

PREFERRED SKILLS AND EXPERIENCE:

• Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub-micron FinFET and CMOS solid state physics
• Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical project milestones

COMPENSATION AND BENEFITS:

Pay range:    
Physical Design Engineer/Level II: $155,000.00 - $185,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

RFIC DESIGN ENGINEER (RFIC ENGINEERING) 

RESPONSIBILITIES: 

• Design, simulate and model RF/analog/mixed-signal circuits and systems 
• Derive specifications for the RFIC subsystems and circuits 
• Develop Analog/Mixed-Signal/RF/microwave circuits in SiGe or CMOS processes 
• Work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains 
• Perform IC floor planning and layout 
• Model package and external parasitic components 
• Evaluate and characterize prototypes of the design 
• Characterize and analyze full radio performance 
• Assist in the development of automated test lab equipment for lab measurements 
• Work with manufacturing engineers on production testing and qualification of the RFIC components and systems 

BASIC QUALIFICATIONS: 

• Bachelor's degree in electrical engineering, computer engineering, or computer science 
• 2+ years of RF integrated circuit experience 

PREFERRED SKILLS AND EXPERIENCE: 

• Master's degree or PhD in electrical engineering or computer engineering with an emphasis in RF/Analog/Mixed-signal integrated circuit design 
• Experience using simulation tools such as Spectre, ADS, HFSS or Momentum 
• Circuit design skills, and experience performing analysis and simulation of both linear and non-linear circuits such as phase-locked loops, vector modulators/demodulators, oscillators, mixers, filters, low noise and power amplifiers 
• Knowledge of digital communication systems, spread spectrum, single and multi-carrier techniques and modulation types such as QPSK, APSK and QAM 
• Knowledge of RF transceiver architectures 
• RF/microwave design in the Ku-band, K-band and Ka-band frequency range 
• Familiarity with radio related test equipment such as spectrum analyzers, vector signal analyzers, vector signal generator, network analyzers 
• Experience characterizing radio performance in microwave frequencies 

ADDITIONAL REQUIREMENTS:  

• Ability to work long hours and weekends as necessary to support critical milestones  

COMPENSATION AND BENEFITS: 

Pay range:     
RF/Analog IC Design Engineer/Level I: $125,000.00 - $145,000.00/per year     
RF/Analog IC Design Engineer/Level II: $145,000.00 - $175,000.00/per year     
 
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. 

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

RTL DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs and participate in integration tasks using Verilog/SystemVerilog
• Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
• Engage in high-level architectural design for FPGA and ASICs
• Collaborate with cross-functional engineers in developing new technologies for the Starlink program impacting User terminals, Satellites, and more

BASIC QUALIFICATIONS:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
• 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL

PREFERRED SKILLS AND EXPERIENCE:

• Master’s in Electrical/Computer Engineering or related field
• ASIC/FPGA system integration experience
• Proficiency in Python for scripting
• Experience in designing DSP or digital communication system datapath blocks
• Experience with EDA tools such as HDL simulators
• Experience and understanding of AXI/AHB/APB protocols
• Strong foundation in electrical engineering fundamentals
• Ability to work in a dynamic environment with changing needs and requirements
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Demonstrated ability to work in a highly cross-functional role
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION & BENEFITS:    

Pay range:    

ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year    
ASIC Design Engineer/Level II: $140,000.00 - $175,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

FALL 2026 ENGINEERING INTERNSHIP/CO-OP

SpaceX seeks extraordinary students to join us for engineering roles in Fall 2026. As an intern, you will work closely with your mentor and other employees who will help you apply your knowledge and grow your skills on projects that have a significant impact. You’ll also get to have some fun and network with other interns and employees through optional social and professional events. If you’ve demonstrated a commitment to academic success and motivation to apply your knowledge outside of the classroom, you are a great candidate!

Internships are available with a variety of engineering teams across the company including design, manufacturing and operations at Bastrop, TX; Cape Canaveral, FL; Hawthorne (Los Angeles), CA; Irvine, CA; McGregor (Waco), TX; Redmond, WA; Starbase, TX and Vandenberg, CA.

BASIC QUALIFICATIONS:

• Must be enrolled in a bachelor’s degree program in an engineering, physics or math discipline by the start of employment
• 3+ months of applied engineering experience (internship, laboratory, and personal/team project experience is applicable)
• Applicant for this intern position must be a (i) U.S. citizen or national, (ii) U.S. lawful permanent resident (e.g., green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158.

PREFERRED SKILLS AND EXPERIENCE:

• GPA of 3.5 or above
• 6+ months experience of application of technical skills outside of the classroom (examples: laboratory, research, extracurricular project teams, volunteering, personal projects or prior internship/work experience)
• Ability to work well in an integrated collaborative team environment, including frequent interactions with technicians, other engineers, and managers
• Ability to work effectively in a dynamic professional setting with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Able to work full time, onsite for a minimum of 12 consecutive weeks beginning in August or September 2026
• Able to provide own transportation for positions at Bastrop, Cape Canaveral, McGregor, and Vandenberg locations

COMPENSATION AND BENEFITS:

Pay range:   

Engineering Intern/Freshman/Sophomore: $28.00/hour
Engineering Intern/Junior/Senior: $30.00/hour

Your salary will be determined by academic level. Pay is just one part of your total rewards package at SpaceX. You may also be eligible for a stipend to subsidize relocation costs, as well as access to our comprehensive medical coverage and a 401(k) retirement plan. Students joining SpaceX through our internship program will receive the opportunity to attend presentations from company leaders, social and networking events, as well as professional and personal development trainings. Interns are also eligible for paid company holidays. SpaceX offers 10 or more paid holidays per year.

PROGRAM DESCRIPTIONS:

DRAGON: Dragon is the most advanced human-rated spacecraft in the world. This capsule currently delivers critical science, cargo and crew safely to and from International Space Station, but further iterations and new designs will likely be necessary to extend humankind's reach to the moon, Mars, and beyond. This program includes roles in: Analysis, Avionics, Build Engineering, Integration & Test Engineering, Life Support Systems, Manufacturing Engineering, Materials Engineering, Propulsion Engineering, Structures Design & Engineering, Supply Chain Engineering and more.

FALCON: The Falcon program tackles space exploration’s toughest problems through the ongoing development of our reusable launch vehicles, Falcon 9 and Falcon Heavy. These vehicles are currently responsible for delivering commercial, national security, and NASA satellites into orbit, as well as supply critical science, supplies, and crew to the International Space Station. This program includes roles in: Analysis, Avionics, Build Engineering, Components Engineering, Integration & Test Engineering, Launch Site Operations & Engineering, Manufacturing Engineering, Materials Engineering, Propulsion Engineering, Recovery Engineering, Structures Design & Engineering, Supply Chain Engineering and more.

STARLINK: At SpaceX, we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to 1M+ users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. This program includes roles in: Analysis, Automation & Controls, Avionics, Components Engineering, Industrial Engineering, Integration & Test Engineering, Manufacturing Engineering, Materials Engineering, Operations Engineering, Structures Design & Engineering, Supply Chain Engineering and more.

STARSHIELD - Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an intern on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. This program includes roles in: Avionics, Build Engineering, Components Engineering, Integration & Test Engineering, Manufacturing Engineering, Materials Engineering, Mechanical Design & Engineering, Structures Engineering, and more.

STARSHIP: The Starship spacecraft and Super Heavy rocket – collectively referred to as Starship – represent a fully reusable transportation system designed to carry both crew and cargo to Earth orbit, the Moon, Mars and beyond. As the most powerful launch system ever developed, Starship will be able to carry up to 100 people on long-duration, interplanetary flights. Starship will also enable satellite delivery, the development of a Moon base and point-to-point transport here on Earth. This program includes roles in: Analysis, Automation & Controls, Avionics, Build Engineering, Civil Engineering, Components Engineering, Industrial Engineering, Launch Site Operations & Engineering, Manufacturing Engineering, Materials Engineering, Propulsion Engineering, Structures Design & Engineering, Supply Chain Engineering, Test Engineering and more.

SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Evaluate architectural trade-offs based on features, performance requirements and system limitations
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
• Work closely with verification team to ensure all aspects of the design are covered and verified
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
• Participate in silicon bring-up and validation

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

• Ability to solve complex problems including clock domain crossings and power optimization
• ASIC/SoC system integration experience
• Experience with embedded CPU subsystems
• Experience with standard bus protocols (e.g. AXI, AHB, etc.)
• Experience with high speed and low power design techniques
• Scripting skills (e.g. Python, etc.)
• Experience with EDA tools such as HDL simulators and HDL Lint tools
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION & BENEFITS:    

Pay range:
ASIC Design Engineer / Senior: $160,000.00 - $225,000.00/per year    
    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. IC PACKAGE DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom in-house ASICs and RFICs for digital beam formers and modems. 

RESPONSIBILITIES:

• Own and drive advanced package selection, new product BGA configuration and package structure
• Responsible for package/SIP layout, optimization, design verification and tapeout
• Interface and coordinate with cross-functional groups throughout SpaceX on new product package selection, feasibility analysis and design
• Work cross-functionally, understand trade-offs, constraints, and optimizing silicon floor plan, bump and package pin out
• Simulate and optimize signal/power integrity and RF performance of the package design
• Drive methodology, innovations, and productivity improvements in package design

BASIC QUALIFICATIONS:

• Bachelor's degree in electrical engineering, computer engineering, or physics
• 5+ years of experience with IC package design

PREFERRED SKILLS AND EXPERIENCE:

• Experience with Co-packaged Optics (CPO)
• Thorough understanding of signal and power integrity fundamentals
• Substrate design experience for RF, digital, high-speed and mixed signal die
• Experience with Cadence APD+/SIP or similar design tools
• Experience in package design electrical review, SI/PI analysis
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, ADS
• Experience in package design for manufacturing reviews
• Familiar with BGA package substrate technologies
• Strong problem solving skills with strong engineering fundamentals

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours or weekends as needed to meet mission critical deadlines

COMPENSATION & BENEFITS:    

Pay range:
RF Engineer/Senior: $160,000.00 - $225,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

RESPONSIBILITIES:  

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks 
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs 
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer science or computer engineering
• 1+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION AND BENEFITS:    
    
Pay range:    
Design Verification Engineer/Level I: $125,000.00 - $145,000.00/per year    
Design Verification Engineer/Level II: $140,000.00 - $175,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Evaluate architectural trade-offs based on features, performance requirements and system limitations
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
• Work closely with verification team to ensure all aspects of the design are covered and verified
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
• Participate in silicon bring-up and validation

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

• Ability to solve complex problems including clock domain crossings and power optimization
• ASIC/SoC system integration experience
• Experience with embedded CPU subsystems
• Experience with standard bus protocols (e.g. AXI, AHB, etc.)
• Experience with high speed and low power design techniques
• Scripting skills (e.g. Python, etc.)
• Experience with EDA tools such as HDL simulators and HDL Lint tools
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION & BENEFITS:    

Pay range:
ASIC Design Engineer / Senior: $160,000.00 - $225,000.00/per year    
    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

RFIC LAYOUT DESIGNER (RFIC ENGINEERING)
At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking motivated, proactive, and intellectually curious engineers who will work alongside world-class cross-disciplinary teams (systems architecture, ASIC design, firmware, pre-silicon verification, post-silicon validation, product engineering, manufacturing/production, and more). In this role, you will be on a team working on multiple silicon projects that are driving more integration, lower power, mixed signal architectures and advanced silicon technology for deployment in space and ground infrastructures. You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs. 

RESPONSIBILITIES:

• Work with the integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging engineer to determine pad locations
• Accurately estimate the schedule for the layout work and identify areas of complexity that need early investigation
• Perform layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitic capacitance in the layout
• Perform design rule checking, electrical rule checking and layout versus schematic checks and resolve errors
• Perform top-level layout integration with electrostatic discharge structures and pad assembly and perform final tape out (including density fill, running design for manufacturability checks and sharing GDS with the foundry)
• Work with EDA suppliers to trial new tools and features
• Generate guides and demos for others in the team to showcase improvements in layout technique

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical or computer engineering and 1+ years of professional experience as an IC layout designer; OR 3+ years of professional experience with integrated circuit layout design in lieu of a degree

PREFERRED SKILLS AND EXPERIENCE:

• Strong analog layout skills
• Experience in advanced node IC layouts such as 22nm, 16nm, 7nm, 5nm or below
• Experience in layout of circuits with frequencies up to 50GHz
• Experience in layout of sensitive RF blocks such as low noise amplifiers, voltage controlled oscillators and mixers
• Experience with skill programming
• Experience with shell scripting, Perl, Python or similar language
• Experience managing revision control systems
• Experience with circuit design
• Understanding of layout considerations for device matching, coupling and noise isolation
• Working knowledge of Linux
• Excellent communication skills (both oral and written) are required
• Able to work independently on challenging problems

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed to meet critical milestones

COMPENSATION AND BENEFITS:    

Pay range:    

Layout Designer/Level I: $105,000.00 - $120,000.00/per year  
Layout Designer/Level II: $115,000.00 - $145,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. RFIC DESIGN ENGINEER

Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As a RFIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation RFICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

RESPONSIBILITIES:

•  Design, simulate and model RF/analog/mixed-signal circuits and systems
•  Derive specifications for the RFIC subsystems and circuits
•  Develop analog/mixed-signal/RF/microwave circuits in SiGe, GaAs, GaN, or CMOS processes
•  Work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains
•  Perform IC floor planning and layout
•  Own packaging prototypes, product development, and release to production. Model package and external parasitic components
•  Evaluate and characterize prototypes of the design
•  Assist in the development of automated test lab equipment for lab measurements
•  Work with manufacturing engineers on production testing and qualification of the RFIC components and systems

BASIC QUALIFICATIONS:

•  Bachelor's degree in electrical engineering, computer engineering, or computer science
•  5+ years of professional RF integrated circuit experience

PREFERRED SKILLS AND EXPERIENCE:

•  Master's degree or PhD in electrical engineering or computer engineering with an emphasis in RF/analog/mixed-signal integrated circuit design
•  Experience using simulation tools such as Spectre, ADS, HFSS or Momentum
•  Circuit design skills, and experience performing analysis and simulation of both linear and non-linear circuits such as phase-locked loops, vector modulators/demodulators, oscillators, mixers, filters, low noise and power amplifiers
•  Knowledge of digital communication systems, spread spectrum, single and multi-carrier techniques and modulation types such as QPSK, APSK and QAM
•  Knowledge of RF transceiver architectures
•  Deep understanding of theory and MMIC design of RF front end blocks, from S-band to W-band frequency ranges
•  Familiarity with radio related test equipment such as spectrum analyzers, vector signal analyzers, vector signal generator, network analyzers
•  Experience characterizing radio performance in microwave frequencies

ADDITIONAL REQUIREMENTS: 

• Ability to work long hours and weekends as necessary to support critical milestones 
• Willingness to travel for off-site testing
• An active clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing

COMPENSATION AND BENEFITS:    
    
Pay range:    

RFIC Engineer/Senior: $160,000.00 - $225,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $20,000 annually, once officially briefed into a classified program.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

RESPONSIBILITIES:  

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks 
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs 
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer science or computer engineering
• 2+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION AND BENEFITS:    
    
Pay range:    
Design Verification Engineer/Level I: $125,000.00 - $145,000.00/per year    
Design Verification Engineer/Level II: $140,000.00 - $175,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

FALL 2026 SOFTWARE ENGINEERING INTERNSHIP/CO-OP

SpaceX seeks extraordinary students to join us for software engineering roles in Fall 2026. As a software intern, you will work closely with your mentor and other employees who will help you apply your knowledge and grow your skills on projects that have a significant impact. You’ll also get to have some fun and network with other interns and employees through optional social and professional events. If you’ve demonstrated a commitment to academic success and motivation to apply your knowledge outside of the classroom, you are a great candidate! Aerospace experience is not required to be successful here - rather we look for smart, motivated, collaborative engineers who love solving problems and want to make an impact on a super inspiring mission.

Internships are available with a variety of software engineering teams across the company at Bastrop, TX; Cape Canaveral, FL; Hawthorne (Los Angeles), CA; Irvine, CA; McGregor (Waco), TX; Redmond, WA; Starbase, TX and Sunnyvale, CA.

BASIC QUALIFICATIONS:

• Must be enrolled in a bachelor’s degree or graduate program by the start of employment
• 3+ months of software programming or development experience
• Software coding experience in one or more of the following: C, C++, C#, Java, JavaScript, Python
• Applicant for this intern position must be a (i) U.S. citizen or national, (ii) U.S. lawful permanent resident (e.g., green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158.

PREFERRED SKILLS AND EXPERIENCE:

• GPA of 3.5 or above
• 6+ months experience developing and deploying software that has been used on real-world applications and projects 
• Strong fundamental knowledge of computer architecture and networks 
• Experience with software documentation, creating system diagrams, and enumerating software requirements
• Strong skills in debugging, performance optimization and unit testing
• Strong interpersonal skills (examples: leading a student organization or working successfully in teams)
• Ability to work effectively in a dynamic environment with changing needs and requirements
• Ability to work independently and in a team, take initiative, and communicate effectively

ADDITIONAL REQUIREMENTS:

• Able to work full time, onsite for a minimum of 12 consecutive weeks beginning in August or September 2026
• Able to provide own transportation for positions at Bastrop, Cape Canaveral, McGregor and Vandenberg locations

COMPENSATION AND BENEFITS:

Pay Range:   

Software Engineering Intern/Freshman/Sophomore: $30.00/hour   
Software Engineering Intern/Junior/Senior: $34.00/hour   
Software Engineering Intern/Completed Bachelor's: $36.00/hour   
Software Engineering Intern/Completed Master's: $38.00/hour   
Software Engineering Intern/Completed PhD: $40.00/hour   

Your salary will be determined by academic level. Pay is just one part of your total rewards package at SpaceX. You may also be eligible for a stipend to subsidize relocation costs, as well as access to our comprehensive medical coverage and a 401(k) retirement plan. Students joining SpaceX through our internship program will receive the opportunity to attend presentations from company leaders, social and networking events, as well as professional and personal development trainings. Interns are also eligible for paid company holidays. SpaceX offers 10 or more paid holidays per year.

TEAM DESCRIPTIONS:

APPLICATION SOFTWARE: The Application software team is currently creating and evolving systems to enable rapid build and reuse of Starship as well as designing the next generation manufacturing software that will be used in high throughput factories for Starlink. Other applications range from platforms that support concurrent streams of data from many always-on assets to manage the world’s largest satellite constellation to public facing systems where customers can join our Starlink network globally. We work closely with engineers throughout the company to create and update our systems with respect to crewed launches, Starship flights, changes to the Starlink network and much more.

DRAGON SOFTWARE: As a software engineering intern on the Dragon Software team, you will develop, analyze and verify the mission critical software configurations that fly our Dragon Crewed and Cargo vehicles. You will partner cross-functionally to ensure software is configured to each mission's specifications and needs. You will be responsible for ensuring the vehicle behaves as expected, and troubleshooting flight software when necessary. You will have a direct impact on our ability to launch and fly vehicles frequently, safely and reliably.

FALCON SOFTWARE: As a software engineering intern on the Falcon Software team, you will develop, analyze and verify the mission critical software that flies our Falcon and Falcon Heavy launch vehicles. You will be responsible for ensuring the vehicle behaves as expected, is adequately tested prior to launches, and troubleshoot flight software when necessary. You will have a direct impact on our ability to launch and fly vehicles frequently, safely and reliably.

GUIDANCE, NAVIGATION & CONTROL (GNC): The GNC teams at SpaceX support our Dragon, Falcon, Starlink, Starshield and Starship programs by developing highly reliable and performant GNC algorithms, simulations, tools, services, and dashboards. The ideal candidates for these teams have experience in orbital mechanics, modeling, and simulation, satellite attitude determination and control, and have a passion for advancing the commercial space industry.

PRODUCT SECURITY: The Starlink Product Security team is seeking technical, passionate engineers to secure Starlink software and hardware. We are looking for people who see the big picture, prioritize accordingly, and are comfortable with working at different levels of abstraction. Ideal candidates have notable skills in one or more of the following: exploit development or mitigation, security architecture design, firmware security, software development, or operating system security.

SILICON ENGINEERING: Designs, develops and qualifies our custom developed semiconductor solutions. The group partners with other engineering teams and industry partners to create innovative digital, analog and mixed-signal ASICs and FPGAs. This group develops a broad variety of chips in CMOS, BiCMOS, GaAs and GaN technologies, from large SoC's to mmWave RFICs. The work includes but is not limited to: system architecture, full flow IC development, RF and PCB development, custom packaging, integration & test, SW development and semiconductor qualification. As an intern, you will have the opportunity of applying your skills in ASIC design, computer architecture, Verilog/SystemVerilog, C/C++, EE/RF circuit design.

STARLINK SOFTWARE: The Starlink software team is solving challenges underpinning every aspect of SpaceX’s satellite internet project, and we’re looking for engineers to join us in building the next-generation networking technologies to direct data through an ever-changing network of satellites, ground stations, and users. The Starlink software team is responsible for the firmware and controls software running on custom hardware that flies the world’s largest fleet of spacecraft, as well as the infrastructure and tools to enable rapid development and reliable deployment of our code to dynamic production environments.

STARSHIELD SOFTWARE: The Starshield software team is building highly reliable in-space mesh networks, designing secure systems to guarantee access to space, designing next-generation communication and sensing software, and more. Aerospace experience is not required to be successful here - we want our engineers to bring fresh, diverse ideas from all areas. The Starshield software team is involved in designing the vehicle systems at every phase of development and building software systems that are secure, reliable, and autonomous. Our software interns are responsible for the life cycle of the software they create, including development, testing, and operational support. 

STARSHIP SOFTWARE: The Starship software team is responsible for building and testing the control systems, network, and operational software for Starship, the Super Heavy Booster, and our launch pads in Starbase. On this team, you will work closely with engineers across the company to prepare our vehicle for its first orbital flights and to lay the groundwork for future crewed flights and human lander programs. Ideal candidates have skills in one or more of the following areas: embedded systems, computer networking, operating systems, or web application development.

SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)

RESPONSIBILITIES:

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering or computer engineering
• 5+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION & BENEFITS:    

Pay range:    
Design Verification Engineer /Senior: $165,000.00 - $230,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. RFIC LAYOUT DESIGNER (RFIC ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking motivated, proactive, and intellectually curious engineers who will work alongside world-class cross-disciplinary teams (systems architecture, ASIC design, firmware, pre-silicon verification, post-silicon validation, product engineering, manufacturing/production, and more). In this role, you will be on a team working on multiple silicon projects that are driving more integration, lower power, mixed signal architectures and advanced silicon technology for deployment in space and ground infrastructures. You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs. 

RESPONSIBILITIES:

• Work with the integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging engineer to determine pad locations
• Accurately estimate the schedule for the layout work and identify areas of complexity that need early investigation
• Perform layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitic capacitance in the layout
• Perform design rule checking, electrical rule checking and layout versus schematic checks and resolve errors
• Perform top-level layout integration with electrostatic discharge structures and pad assembly and perform final tape out (including density fill, running design for manufacturability checks and sharing GDS with the foundry)
• Work with EDA suppliers to trial new tools and features
• Generate guides and demos for others in the team to showcase improvements in layout technique

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical or computer engineering and 5+ years of professional experience as an IC layout designer; OR 8+ years of professional experience with integrated circuit layout design in lieu of a degree

PREFERRED SKILLS AND EXPERIENCE:

• Strong analog layout skills
• Experience in advanced node IC layouts such as 22nm, 16nm, 7nm, 5nm or below
• Experience in layout of circuits with frequencies up to 50GHz
• Experience in layout of sensitive RF blocks such as low noise amplifiers, voltage controlled oscillators and mixers
• Experience with skill programming
• Experience with shell scripting, Perl, Python or similar language
• Experience managing revision control systems
• Experience with circuit design
• Understanding of layout considerations for device matching, coupling and noise isolation
• Working knowledge of Linux
• Excellent communication skills (both oral and written) are required
• Able to work independently on challenging problems

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed to meet critical milestones

COMPENSATION AND BENEFITS:    

Pay range:    
RFIC Layout Designer/Senior: $135,000.00 - $195,000.00/per year    
    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

PRINCIPAL DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)

RESPONSIBILITIES:

• Responsible for digital ASIC and/or FPGA verification at block and system level
• Lead and execute verification test plan, development, and milestones from beginning to end
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 10+ years of experience with design verification and test bench development
• 10+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION & BENEFITS:    

Pay range:    
Design Verification Engineer / Principal: $210,000.00 - $300,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. RFIC DESIGN ENGINEER (RFIC ENGINEERING) 

RESPONSIBILITIES: 

• Design, simulate and model RF/analog/mixed-signal circuits and systems 
• Derive specifications for the RFIC subsystems and circuits 
• Develop Analog/Mixed-Signal/RF/microwave circuits in SiGe or CMOS processes 
• Work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains 
• Perform IC floor planning and layout 
• Model package and external parasitic components 
• Evaluate and characterize prototypes of the design 
• Characterize and analyze full radio performance 
• Assist in the development of automated test lab equipment for lab measurements 
• Work with manufacturing engineers on production testing and qualification of the RFIC components and systems

BASIC QUALIFICATIONS: 

• Bachelor's degree in electrical engineering, computer engineering, or computer science 
• 5+ years of RF integrated circuit experience 

PREFERRED SKILLS AND EXPERIENCE: 

• Master's degree or PhD in electrical engineering or computer engineering with an emphasis in RF/Analog/Mixed-signal integrated circuit design 
• Experience using simulation tools such as Spectre, ADS, HFSS or Momentum 
• Circuit design skills, and experience performing analysis and simulation of both linear and non-linear circuits such as phase-locked loops, vector modulators/demodulators, oscillators, mixers, filters, low noise and power amplifiers 
• Knowledge of digital communication systems, spread spectrum, single and multi-carrier techniques and modulation types such as QPSK, APSK and QAM 
• Knowledge of RF transceiver architectures 
• RF/microwave design in the Ku-band, K-band and Ka-band frequency range 
• Familiarity with radio related test equipment such as spectrum analyzers, vector signal analyzers, vector signal generator, network analyzers 
• Experience characterizing radio performance in microwave frequencies 

ADDITIONAL REQUIREMENTS:  

• Ability to work long hours and weekends as necessary to support critical milestones  

COMPENSATION AND BENEFITS: 

Pay range:     
RF/Analog IC Design Engineer/Senior: $160,000.00 - $225,000/per year     
 
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. 

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.