PHYSICAL DESIGN ENGINEER II (SILICON ENGINEERING)

RESPONSIBILITIES:

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

PREFERRED SKILLS AND EXPERIENCE:

• Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub-micron FinFET and CMOS solid state physics
• Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical project milestones

PHYSICAL DESIGN ENGINEER II (SILICON ENGINEERING)

RESPONSIBILITIES:

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

PREFERRED SKILLS AND EXPERIENCE:

• Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub-micron FinFET and CMOS solid state physics
• Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical project milestones

COMPENSATION AND BENEFITS:

Pay range:    
Physical Design Engineer/Level II: $155,000.00 - $185,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

PHYSICAL DESIGN ENGINEER II (SILICON ENGINEERING)

RESPONSIBILITIES:

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

PREFERRED SKILLS AND EXPERIENCE:

• Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub-micron FinFET and CMOS solid state physics
• Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical project milestones

COMPENSATION AND BENEFITS:

Pay range:    
Physical Design Engineer/Level II: $145,000.00 - $175,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
• Develop, maintain, and optimize physical verification flows for advanced node SoC’s.
• Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes
• Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
• Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
• Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
• Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
• Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE:

• Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
• Experience in IP integration (e.g. memories, I/O’s, analog IPs, SerDes, DDR etc.)
• Deep expertise in DRC, LVS, PERC and ESD verification methodologies
• Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
• Direct foundry DRM experience — able to read, interpret, and implement complex rule decks
• Experience at advanced nodes (4nm and below)
• Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
• Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:    

• Ability to work extended hours and weekends as needed to meet critical project milestones    

SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
• Develop, maintain, and optimize physical verification flows for advanced node SoC’s.
• Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes
• Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
• Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
• Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
• Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
• Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE:

• Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
• Experience in IP integration (e.g. memories, I/O’s, analog IPs, SerDes, DDR etc.)
• Deep expertise in DRC, LVS, PERC and ESD verification methodologies
• Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
• Direct foundry DRM experience — able to read, interpret, and implement complex rule decks
• Experience at advanced nodes (4nm and below)
• Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
• Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:    

• Ability to work extended hours and weekends as needed to meet critical project milestones    

COMPENSATION AND BENEFITS:

Pay range:    
Physical Design Engineer/Senior: $170,000.00 - $230,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

RESPONSIBILITIES:  

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks 
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs 
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer science or computer engineering
• 1+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION AND BENEFITS:    
    
Pay range:    
Design Verification Engineer/Level I: $125,000.00 - $145,000.00/per year    
Design Verification Engineer/Level II: $145,000.00 - $175,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

PRINCIPAL DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)

RESPONSIBILITIES:

• Responsible for digital ASIC and/or FPGA verification at block and system level
• Lead and execute verification test plan, development, and milestones from beginning to end
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 10+ years of experience with design verification and test bench development
• 10+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION & BENEFITS:    

Pay range:    
Design Verification Engineer / Principal: $210,000.00 - $300,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Evaluate architectural trade-offs based on features, performance requirements and system limitations
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
• Work closely with verification team to ensure all aspects of the design are covered and verified
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
• Participate in silicon bring-up and validation

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

• Ability to solve complex problems including clock domain crossings and power optimization
• ASIC/SoC system integration experience
• Experience with multicore CPU subsystem design
• Experience with standard bus protocols (e.g. AXI, AHB, etc.)
• Experience with embedded processors
• Experience with high speed and low power design techniques
  
• Scripting skills (Python, TCL etc.)
• Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
• Ability to work in a dynamic environment with changing needs and requirements
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION & BENEFITS:    

Pay range:
ASIC Design Engineer/Senior: $160,000.00 - $225,000.00/per year    
    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

RTL DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs and participate in integration tasks using Verilog/SystemVerilog
• Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
• Engage in high-level architectural design for FPGA and ASICs
• Collaborate with cross-functional engineers in developing new technologies for the Starlink program impacting User terminals, Satellites, and more

BASIC QUALIFICATIONS:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
• 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL

PREFERRED SKILLS AND EXPERIENCE:

• Master’s in Electrical/Computer Engineering or related field
• ASIC/FPGA system integration experience
• Proficiency in Python for scripting
• Experience in designing DSP or digital communication system datapath blocks
• Experience with EDA tools such as HDL simulators
• Experience and understanding of AXI/AHB/APB protocols
• Strong foundation in electrical engineering fundamentals
• Ability to work in a dynamic environment with changing needs and requirements
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Demonstrated ability to work in a highly cross-functional role
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION & BENEFITS:    

Pay range:    

ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year    
ASIC Design Engineer/Level II: $140,000.00 - $175,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Evaluate architectural trade-offs based on features, performance requirements and system limitations
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
• Work closely with verification team to ensure all aspects of the design are covered and verified
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
• Participate in silicon bring-up and validation

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

• Ability to solve complex problems including clock domain crossings and power optimization
• ASIC/SoC system integration experience
• Experience with embedded CPU subsystems
• Experience with standard bus protocols (e.g. AXI, AHB, etc.)
• Experience with high speed and low power design techniques
• Scripting skills (e.g. Python, etc.)
• Experience with EDA tools such as HDL simulators and HDL Lint tools
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours or weekends as needed for mission critical deadlines

RESPONSIBILITIES:  

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks 
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs 
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer science or computer engineering
• 2+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical milestones

COMPENSATION AND BENEFITS:    
    
Pay range:    
Design Verification Engineer/Level I: $135,000.00 - $155,000.00/per year    
Design Verification Engineer/Level II: $155,000.00 - $185,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Evaluate architectural trade-offs based on features, performance requirements and system limitations
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
• Work closely with verification team to ensure all aspects of the design are covered and verified
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
• Participate in silicon bring-up and validation

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

• Ability to solve complex problems including clock domain crossings and power optimization
• ASIC/SoC system integration experience
• Experience with multicore CPU subsystem design
• Experience with standard bus protocols (e.g. AXI, AHB, etc.)
• Experience with embedded processors
• Experience with high speed and low power design techniques
  
• Scripting skills (Python, TCL etc.)
• Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
• Ability to work in a dynamic environment with changing needs and requirements
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical milestones

COMPENSATION & BENEFITS:    

Pay range:
ASIC Design Engineer/Senior: $170,000.00 - $235,000.00/per year    
    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

PRINCIPAL DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)

RESPONSIBILITIES:

• Responsible for digital ASIC and/or FPGA verification at block and system level
• Lead and execute verification test plan, development, and milestones from beginning to end
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 10+ years of experience with design verification and test bench development
• 10+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical milestones

COMPENSATION & BENEFITS:    

Pay range:    
Design Verification Engineer / Principal: $210,000.00 - $310,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Evaluate architectural trade-offs based on features, performance requirements and system limitations
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
• Work closely with verification team to ensure all aspects of the design are covered and verified
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
• Participate in silicon bring-up and validation

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

• Ability to solve complex problems including clock domain crossings and power optimization
• ASIC/SoC system integration experience
• Experience with embedded CPU subsystems
• Experience with standard bus protocols (e.g. AXI, AHB, etc.)
• Experience with high speed and low power design techniques
• Scripting skills (e.g. Python, etc.)
• Experience with EDA tools such as HDL simulators and HDL Lint tools
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION & BENEFITS:    

Pay range:
ASIC Design Engineer / Senior: $160,000.00 - $225,000.00/per year    
    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

RF SILICON SOFTWARE ENGINEER (STARLINK)

SpaceX is looking for engineers with backgrounds in electrical engineering and software development to bring new silicon to life. The ideal candidate will have real-world experience in multiple areas that span the hardware/software boundary: RF measurements, automation software, hardware development, and embedded firmware. You will be part of a multidisciplinary team focused on solving challenging problems related to the silicon used in all terrestrial/space-based elements of a high-performance wireless digital communication system. You will join a team with “extreme ownership” of the silicon life-cycle, from system requirements, to chip design, to characterization, to production ramp-up, to on-orbit telemetry monitoring.

RESPONSIBILITIES:

As an engineer on the RFIC team, you will solve challenging problems related to all aspects of the RF silicon that we design in-house. Much of the measurement system software and hardware that you create will be first-generation, supporting RF/RFIC designs well into the future.

• Design and build unique and technically-challenging automated measurement systems in ways that off-the-shelf equipment may not be capable of capturing. Often this involves creating both new hardware and software designs.
• Bring up new silicon, often being the first engineer to power on chips for the very first time
• Develop tools and reusable libraries for instrument control, data collection and analysis of the radio subsystems
• Deeply understand measurement data to gain insight into both component and system performance
• Create fully-validated reference designs (both hardware and software drivers) for new silicon, and support integration into downstream areas such as phased-array panel bring-up, production, and flight software

BASIC QUALIFICATIONS:

• Bachelor’s degree in computer science, computer engineering, electrical engineering or physics
• 1+ years of experience in software development in a high level language like C#, Python, or C++

PREFERRED SKILLS AND EXPERIENCE:

• MS or PhD in computer science, computer engineering, electrical engineering or physics
• Strong communication skills and ability to work well within a fast-paced team
• Hands-on experience with radio-related test equipment such as spectrum analyzers, vector signal analyzers, vector signal generators, and network analyzers
• Experience with serial digital communication protocols such as SPI, I2C, JTAG, RFFE, software/hardware solutions to exercise these, and hands-on experience troubleshooting with oscilloscopes and logic analyzers
• Experience with Python, MATLAB or JMP for data analysis
• Experience with microcontrollers, FPGAs, and/or basic digital signal processing concepts
• Strong troubleshooting and debugging skills (both software and hardware)
• Experience designing, fabricating, and assembling quick-turn PCBs
• Experience with data management, analysis, and presentation techniques
• Knowledge of statistical concepts and techniques
• Experience developing multi-threaded applications and systems
• Experience with both Windows and Linux system usage/administration

ADDITIONAL REQUIREMENTS:

• Willing to work extended hours and weekends as needed to meet critical milestones

COMPENSATION AND BENEFITS:             

Pay range:    
RF Silicon Software Engineer/Level I: $122,500 - $145,000/per year    
RF Silicon Software Engineer/Level II: $140,000 - $170,000/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. IC PACKAGE DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom in-house ASICs and RFICs for digital beam formers and modems. 

RESPONSIBILITIES:

• Own and drive advanced package selection, new product BGA configuration and package structure
• Responsible for package/SIP layout, optimization, design verification and tapeout
• Interface and coordinate with cross-functional groups throughout SpaceX on new product package selection, feasibility analysis and design
• Work cross-functionally, understand trade-offs, constraints, and optimizing silicon floor plan, bump and package pin out
• Simulate and optimize signal/power integrity and RF performance of the package design
• Drive methodology, innovations, and productivity improvements in package design

BASIC QUALIFICATIONS:

• Bachelor's degree in electrical engineering, computer engineering, or physics
• 5+ years of experience with IC package design

PREFERRED SKILLS AND EXPERIENCE:

• Experience with Co-packaged Optics (CPO)
• Thorough understanding of signal and power integrity fundamentals
• Substrate design experience for RF, digital, high-speed and mixed signal die
• Experience with Cadence APD+/SIP or similar design tools
• Experience in package design electrical review, SI/PI analysis
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, ADS
• Experience in package design for manufacturing reviews
• Familiar with BGA package substrate technologies
• Strong problem solving skills with strong engineering fundamentals

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours or weekends as needed to meet mission critical deadlines

COMPENSATION & BENEFITS:    

Pay range:
RF Engineer/Senior: $160,000.00 - $225,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. ASIC VALIDATION ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Perform pre-silicon emulation of critical systems of next-generation ASICs
• Work within a small team of validation engineers to rapidly develop and bring up custom SpaceX silicon
• Design, build, validate, and automate test benches for full characterization of custom silicon
• Work closely with the FPGA/ASIC Design, Flight Software, and Satellite Engineering teams, to add/improve testability and define various test infrastructure logic to ensure adequate silicon test coverage
• Design and build modular, reusable instrument driver libraries and test automation sequences in C/C++ or Python

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, computer science, or physics
• 5+ years of experience developing ASICs or FPGAs

PREFERRED SKILLS AND EXPERIENCE:

• Master's degree in electrical engineering, computer engineering, computer science, or physics
• Experience with microcontrollers, FPGAs, and/or basic digital signal processing concepts
• Experience using one or more emulation or prototyping platforms from a major EDA vendor (e.g. Palladium, Veloce, ZeBu, etc.)
• Ability to analyze internal and external test results to help drive IP selections for future products
• Experience writing comprehensive test reports covering test boundary conditions and test results for internal technical audiences
• Strong communication skills and ability to work well within a fast-paced team
• Experience working with various high-speed SerDes architectures (NRZ, PAM4) and various clocking modes
• Experience with Ethernet, PCIe and other high-speed protocol layers
• Experience with serial digital communication protocols such as SPI, I2C, JTAG and/or the software/hardware solutions to exercise these
• Experience developing multi-threaded applications and systems
• Experience with both Windows and Linux system usage/administration
• Experience troubleshooting interactions between software and hardware such as network devices and lab instrumentation
• Experience with configuration management and version control software
• Strong debugging and problem-solving skills
• Strong object-oriented programming skills

ADDITIONAL REQUIREMENTS:    

• Must be willing to work extended hours and weekends as needed

COMPENSATION AND BENEFITS:

Pay range:    
ASIC Validation Engineer/Senior: $160,000.00 - $225,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

PRINCIPAL DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)

RESPONSIBILITIES:

• Responsible for digital ASIC and/or FPGA verification at block and system level
• Lead and execute verification test plan, development, and milestones from beginning to end
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 10+ years of experience with design verification and test bench development
• 10+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION & BENEFITS:    

Pay range:    
Design Verification Engineer/Principal: $210,000.00 - $300,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. RFIC DESIGN ENGINEER (SILICON ENGINEERING) 

RESPONSIBILITIES: 

• Design, simulate and model RF/analog/mixed-signal circuits and systems 
• Derive specifications for the RFIC subsystems and circuits 
• Develop Analog/Mixed-Signal/RF/microwave circuits in SiGe or CMOS processes 
• Work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains 
• Perform IC floor planning and layout 
• Model package and external parasitic components 
• Evaluate and characterize prototypes of the design 
• Characterize and analyze full radio performance 
• Assist in the development of automated test lab equipment for lab measurements 
• Work with manufacturing engineers on production testing and qualification of the RFIC components and systems

BASIC QUALIFICATIONS: 

• Bachelor's degree in electrical engineering, computer engineering, or computer science 
• 5+ years of RF integrated circuit experience 

PREFERRED SKILLS AND EXPERIENCE: 

• Master's degree or PhD in electrical engineering or computer engineering with an emphasis in RF/Analog/Mixed-signal integrated circuit design 
• Experience using simulation tools such as Spectre, ADS, HFSS or Momentum 
• Circuit design skills, and experience performing analysis and simulation of both linear and non-linear circuits such as phase-locked loops, vector modulators/demodulators, oscillators, mixers, filters, low noise and power amplifiers 
• Knowledge of digital communication systems, spread spectrum, single and multi-carrier techniques and modulation types such as QPSK, APSK and QAM 
• Knowledge of RF transceiver architectures 
• RF/microwave design in the Ku-band, K-band and Ka-band frequency range 
• Familiarity with radio related test equipment such as spectrum analyzers, vector signal analyzers, vector signal generator, network analyzers 
• Experience characterizing radio performance in microwave frequencies 

ADDITIONAL REQUIREMENTS:  

• Ability to work long hours and weekends as necessary to support critical milestones  

COMPENSATION AND BENEFITS: 

Pay range:     
RF/Analog IC Design Engineer/Senior: $170,000.00 - $230,000/per year     
 
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. 

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Evaluate architectural trade-offs based on features, performance requirements and system limitations
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
• Work closely with verification team to ensure all aspects of the design are covered and verified
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
• Participate in silicon bring-up and validation

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

• Ability to solve complex problems including clock domain crossings and power optimization
• ASIC/SoC system integration experience
• Experience with multicore CPU subsystem design
• Experience with standard bus protocols (e.g. AXI, AHB, etc.)
• Experience with embedded processors
• Experience with high speed and low power design techniques
  
• Scripting skills (Python, TCL etc.)
• Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
• Ability to work in a dynamic environment with changing needs and requirements
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical milestones

COMPENSATION & BENEFITS:    

Pay range:
ASIC Design Engineer/Senior: $170,000.00 - $235,000.00/per year    
    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

RESPONSIBILITIES:  

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks 
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs 
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer science or computer engineering
• 2+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION AND BENEFITS:    
    
Pay range:    
Design Verification Engineer/Level I: $125,000.00 - $145,000.00/per year    
Design Verification Engineer/Level II: $140,000.00 - $175,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Evaluate architectural trade-offs based on features, performance requirements and system limitations
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
• Work closely with verification team to ensure all aspects of the design are covered and verified
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
• Participate in silicon bring-up and validation

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

• Ability to solve complex problems including clock domain crossings and power optimization
• ASIC/SoC system integration experience
• Experience with embedded CPU subsystems
• Experience with standard bus protocols (e.g. AXI, AHB, etc.)
• Experience with high speed and low power design techniques
• Scripting skills (e.g. Python, etc.)
• Experience with EDA tools such as HDL simulators and HDL Lint tools
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION & BENEFITS:    

Pay range:
ASIC Design Engineer / Senior: $160,000.00 - $225,000.00/per year    
    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

PRINCIPAL DFT ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
• Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
• Run and debug non-timing and SDF annotated gate level simulations
• Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C+

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 10+ years of experience working with ASICs
• 10+ years of experience in scan insertion and DFT setup, integration and validation

PREFERRED SKILLS AND EXPERIENCE:

• Leadership experience driving SOC DFT execution from concept through tapeout and product deployment
• RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT
• Ability to solve complex problems including clock domain crossings and power optimization
• Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
• Familiar with advanced silicon process and technology nodes for high speed and low power consumption
• Strong implementation or integration of design blocks using Verilog/SystemVerilog
• Experience working with ATE testers and test teams

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical milestones   

COMPENSATION AND BENEFITS:

Pay range:    
Physical Design Engineer/Principal: $210,000.00 - $295,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)

RESPONSIBILITIES:

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering or computer engineering
• 5+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION & BENEFITS:    

Pay range:    
Design Verification Engineer /Senior: $170,000.00 - $230,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)

RESPONSIBILITIES:

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering or computer engineering
• 5+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION & BENEFITS:    

Pay range:    
Design Verification Engineer /Senior: $165,000.00 - $230,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. SOC VERIFICATION ENGINEER (SILICON ENGINEERING)

RESPONSIBILITIES:

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering or computer engineering
• 5+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION & BENEFITS:    

Pay range:    
Design Verification Engineer/Senior: $175,000.00 - $240,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

RESPONSIBILITIES:  

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks 
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs 
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer science or computer engineering
• 1+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION AND BENEFITS:    
    
Pay range:    
Design Verification Engineer/Level I: $125,000.00 - $145,000.00/per year    
Design Verification Engineer/Level II: $140,000.00 - $175,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. RF SILICON SOFTWARE ENGINEER (RFIC Engineering)

SpaceX is looking for engineers with backgrounds in electrical engineering and software development to bring new silicon to life. The ideal candidate will have real-world experience in multiple areas that span the hardware/software boundary: RF measurements, automation software, hardware development, and embedded firmware. You will be part of a multidisciplinary team focused on solving challenging problems related to the silicon used in all terrestrial/space-based elements of a high-performance wireless digital communication system. You will join a team with “extreme ownership” of the silicon life-cycle, from system requirements, to chip design, to characterization, to production ramp-up, to on-orbit telemetry monitoring.

RESPONSIBILITIES:

As an engineer on the RFIC team, you will solve challenging problems related to all aspects of the RF silicon that we design in-house. Much of the measurement system software and hardware that you create will be first-generation, supporting RF/RFIC designs well into the future.

• Bring up new RF silicon as the first engineer to power on chips for the very first time
• Design and build modular, reusable software driver libraries for low-level silicon control with special attention to timing, throughput, performance, and simplicity
• Design and build hardware test platforms (hardware-in-the-loop/HTIL/HIL), and validate silicon driver software on physical hardware or FPGA emulators
• Support software integration into multiple project-specific flight software teams such as satellite phased-arrays and user terminal production

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 5+ years of professional development experience in C, C++, or Python

PREFERRED SKILLS AND EXPERIENCE:

• Professional experience developing, debugging, and deploying software that has been used in real-world applications or projects
• Solid engineering fundamentals and knowledge of electronics, math, physics, and RF communication systems
• Strong skills in debugging, performance optimization, and unit testing
• Creative approach to problem-solving and exceptional analytical skills 
• Excellent communication skills both written and verbal
• Ability to work effectively in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed to meet critical milestones  

COMPENSATION AND BENEFITS:    

Pay range:    
RF Silicon Software Engineer/Senior: $160,000.00 - $225,000.00/per year    
    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

RESPONSIBILITIES:  

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs 
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs 
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer science or computer engineering
• 2+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical milestones

COMPENSATION AND BENEFITS:    
    
Pay range:    
Design Verification Engineer/Level I: $135,000.00 - $155,000.00/per year    
Design Verification Engineer/Level II: $155,000.00 - $185,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)

RESPONSIBILITIES:

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering or computer engineering
• 5+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM/OVM/VMM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION & BENEFITS:    

Pay range:    
Design Verification Engineer /Senior: $165,000.00 - $230,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.