We are looking for a talented engineer to join our CPU design team and lead the front-end RTL physical implementation team. Drive CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An expert in physical design practices used to optimize PPA
• Experienced in high-performance physical design.
• Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis.
• Skilled in synthesis, place and route tools including flows and physical design methodology.
• Background in CPU micro-architecture.

What We Need

• Own front‑end physical implementation and PPA definition for a high‑performance RISC‑V CPU and CPU subsystem 
• Work closely with microarchitects and RTL designers to “make the IP better” by optimizing frequency, power, and area across process nodes
• Define initial floorplans and early area, power, and frequency estimates for key CPU and subsystem configurations
• Partner with the broader PD organization and PD leads to improve and standardize methodologies, flows, and customer collateral for CPU, subsystem, and system IPs, acting as a “PD for IP” specialist bridging PD and design teams
• Use innovative techniques to optimize power, performance, and area while driving physical design experiments and evaluating results.
• Summarize and communicate PPA trade‑offs and recommendations to the broader RISC‑V and PD teams

What You Will Learn

• Develop and lead a high performance physical design team tailored to solving difficult and unique problems to generate leading IP solutions
• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• Hands-on experience optimizing CPU designs and driving PPA improvement.
• Integration of open-source and industry-standard tools to improve physical flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.