NVIDIA's Silicon Co-Design Group (SCG) sits at the intersection of architecture, silicon, systems, and manufacturing — where engineering judgment at the highest level drives real-world product outcomes at scale. 

We are hiring a Senior TPM who doesn't just lead programs but shapes them: A Senior TPM who has owned SoC programs from architecture through tape-out, bring-up, and productization—not by coordinating meetings, but by owning outcomes, schedules, and trade-offs. They combine deep hands-on knowledge of bring-up and validation with the judgment to see integration risks across silicon, systems, and software, and they drive alignment across engineering, operations, and product without deferring hard calls. They operate effectively when requirements and architecture are still changing. They identify dependencies and misalignment early, before crises develop. They close risks with mitigation plans that engineers respect. They improve how the organization completes work after each program. They are credible on silicon hardware logistics (silicon, boards, peripherals), so validation and bring-up stay unblocked. The exceptional hire also uses AI deliberately: they have hands-on experience with AI-powered program management tools (e.g., automated status, risk, and dependency signals) and can tell what improves outcomes versus what adds noise. This role requires on-site teamwork in Santa Clara, a minimum of three days per week.

What you'll be doing:

• Own program outcomes end-to-end — define and manage schedules, surface dependencies before they block work, and drive multi-functional alignment from architecture review through tape-out and bring-up; you’re accountable for delivery, not only oversight.

• Lead through design complexity — take part in critical design reviews, flag scope risks early, resolve them with minimal disruption, and make trade-off calls others will depend on.

• Be the connective tissue — act as the main technical link among silicon, systems, software, operations, and marketing; keep teams aligned on program goals and GTM needs, and catch misalignment before it hurts the program.

• Drive risk to closure — find technical and schedule risks early, build mitigations with engineering, and move work forward with clarity and context, not only status.

• Raise the execution bar — capture lessons from finished programs and put in place process changes that measurably improve speed, quality, and predictability on later programs.

• Handle silicon hardware logistics — coordinate movement, tracking, and availability of silicon, boards, and peripherals so validation and bring-up stay unblocked.

What we need to see:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent experience); a master’s is a plus

• 12+ years in technical roles, with at least 5 years in technical program management — ideally driving SoC programs from bring-up through productization

• Deep, hands-on understanding of SoC bring-up, validation, and productization — you know the stages, what each involves, and what can go wrong

• Ability to work across the silicon–system–software boundary — enough depth in each area to spot integration risks and drive fixes without having to be the expert on every technical question

• Proven track record to run fast development cycles in uncertainty — you develop transparency instead of waiting for it

• Communication that is precise, direct, and right-sized for the audience

• On-site in Santa Clara, CA, a minimum of three days per week

Ways to stand out from the crowd:

• Used AI-style program management tools (e.g., automated status, risk flagging, dependency tracking) and can tell which tools help outcomes vs add noise

• Experience working with AI/ML teams on inference infrastructure and aligning multi-functional work with go-to-market timing for AI-accelerated products

• Experience with AI-assisted logistics tracking to speed bring-up and reduce manual efforts, including where those approaches stop being reliable

• Can evaluate and help roll out new AI productivity tools (coding assistants, automated documentation) and make a clear case for what actually improves engineering velocity