NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing. As an NVIDIAN, you will address challenges spanning architecture, silicon, firmware, software, and production — and excellent judgment matters as much as technical depth! We are the Silicon Power Team within the Silicon Co-Design Group. We architect and deliver groundbreaking solutions for productizing NVIDIA's chips across consumer, professional, server, embedded, mobile, and automotive markets. Silicon characterization, correlation to arch and design expectations, product spec finalization, and productization techniques and infrastructure are our day-to-day work — always on the bleeding edge of the industry. Small decisions here have outsized impact on performance, efficiency, reliability, bring-up speed, and ultimately what the product delivers in the field.

We are hiring a Senior Silicon Power Engineer to own power-feature productization on a flagship silicon program. This is not a coordination role, and it is not a compliance role — it is the seat where power features either work at scale or become the reason a program slips. The two highest-leverage problems in this seat:

• Close the hardest multi-functional power failures before they gate a program. Take ambiguous, cross-boundary issues across architecture, firmware, validation, and platform to root-cause closure — with productized fixes and reusable methodology the next program can inherit.

• Build AI-enabled characterization as a real capability, not a demo. Every bring-up generates terabytes of characterization, shmoo, and telemetry data. Deploy AI workflows for data analysis, metric extraction, trend detection, and cross-bring-up correlation — with the guardrails and validation discipline to make them trustworthy enough to gate production decisions!

What you’ll be doing:

• Lead the effort across architecture, validation, firmware, software, and production teams to keep the program's power and low-power productization strategy clear, executable, and on track.

• Characterize and validate new power-saving features, debug silicon issues, and work with SW/FW teams to productize industry-defining capabilities.

• Resolve complex silicon issues through structured hypotheses, measurement plans, and root-cause closure — and codify the fixes as reusable methodology across programs.

• Design and deploy AI-enabled workflows to automate data analysis, metric extraction, trend checks, and report generation across multiple bring-ups — with explicit guardrails and measurable workflow impact.

• Serve as the key technical owner for multi-functional decisions, issues, and tradeoffs across power, thermal, performance, firmware, and schedule constraints.

• Partner with globally distributed teams — system architects, chip and board designers, SW/FW engineers, applications, reliability specialists, ATE engineers, and PMs — including counterpart engineers in India and other major hubs.

What we need to see:

• BS + 5 years, or MS + 4 years, in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience), with a proven track record in post-silicon bring-up and validation of silicon power features on complex ASIC or SoC programs.

• Deep hands-on expertise in power-saving mechanisms, power characterization, tester-to-system correlation, and lab fundamentals (oscilloscopes, DMM, DAQ, debuggers) — with at least one specific example of taking an ambiguous power failure to root-cause closure with a productized fix.

• Strong end-to-end understanding of silicon behavior across architecture, firmware, validation, and platform interactions, and a demonstrated ability to make sound tradeoff decisions across power, thermal, performance, firmware, design, validation, and schedule constraints.

• Demonstrated AI-enabled workflow you built or scaled for silicon characterization or validation — with adoption beyond yourself, measurable workflow impact, and clear validation discipline, observability, and guardrails.

Ways to stand out from the crowd:

• Deep hands-on subsystem expertise across Windows and Linux low-power states, silicon power behavior, transistor/device physics, silicon reliability, and aging mechanisms — including original power-analysis methodology adopted by other programs.

• Silicon-level impact you personally drove — faster bring-up, stronger characterization coverage, better debug turnaround, or methodology improvements that reduced risk across programs, backed by artifacts, patents, or published technical work.

• Experience partnering deeply with a counterpart team in India or another major engineering hub — shared on-call, shared metrics, and shared culture across geographies.

• AI work that goes beyond personal-copilot use — agentic workflows, RAG-grounded debug assistants, ML-driven characterization analytics, or automated trend detection — deployed at team scope with adoption metrics

If you want to solve ambiguous silicon problems, build original methodology rather than inherit it, and use AI with the rigor required for production decisions, this role offers unusually broad ownership and unusually high leverage ! We are looking for someone who improves how NVIDIA characterizes, validates, and productizes power features across ASIC programs.

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