Your responsibilities:

• Take ownership and responsibility of the verification of one or more submodules owned by the team, including verification IPs and testbenches at different level of integration;

• Review, understand and discuss subsystem/submodules requirements and design specifications at each new functional or technology increment;

• Collaborate with the subsystem architect and discipline leads in the definition of an integrated and consistent verification strategy; collaborate with the DV team mates in breaking down the strategy into activities and tasks, supporting planning activities with the identification of effort and priorities;

• Define and document metrics and the methodology required to assess the completion of the verification campaign; support the definition and the specifications of any testbench component;

• Track and document the whole verification activity with respect to the adopted process and the requirements; create or update the verification specs and reports at each project phase review;

• Interact with peers, HW and SW designers, and system engineers for a quick analysis and resolution of any issue, bug or support request;

• Contribute to the maintenance and documentation of the digital verification (DV) process, as well as to any methodology update or improvements of the whole DV team;

• Keep yourself updated with latest verification methodology and tools by following courses, seminars, webinars and literature.

Your profile:

• University Degree (Master or PhD) in Electrical/Electronic Engineering, Computer Science or equivalent;

• At least eight years of proven professional experience in Digital Design and Verification;

• System Verilog and UVM Methodology training certifications from EDA vendors;

• Familiarity with ASIC / SoC design flow and process.

• Advanced knowledge of Verilog and System Verilog languages (VHDL is a plus);

• Proven experience in testbench design and development using UVM methodology;

• High proficiency in Metric Driven Verification concepts, functional and code coverage;

• High proficiency in directed and constrained random methodologies;

• Advanced knowledge of formal verification methodologies and assertions;

• Proficiency with languages used for testcases development: bash/tcsh, tcl, Python and C;

• Good experience with Centralized Version Control Systems (e.g. SVN, GIT, Clearcase);

• Comfortable at working in a collaborative and technically demanding team/group;

• Very good spoken and written English skills.

Please note: The successful candidate may/will be responsible for security related tasks. The assignment may/will be in scope of security certifications, therefore a conscious and reliable way of working is necessary.

For applications in Gratkorn: NXP provides market competitive compensation according to the benchmarking of the electronic and semiconductor industry. Due to the Austrian Equal Treatment Act we are obligated to state the employment group of our applicable collective bargaining agreement (CBA) “Kollektivvertrag für Angestellte Gewerbe und Handwerk und in der Dienstleistung“, this position (fulltime) is graded in Employment Group V after 6 years. Your individual experiences and expectations will be considered in the application process. Moreover, we provide attractive benefits to our employees like home office, flexible working time, meal benefits and more.

More information about NXP in Austria...