At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Role Overview:

Work closely with R&D and drive timing signoff and ECO for advanced SoCs using industry-standard tools such as Tempus/Certus. Contribute to advanced-node enablement and emerging AI-driven workflows.

 Key Responsibilities:

- Perform static timing analysis across MMMC scenarios (block and full-chip)

- Debug setup/hold violations, SI, and variation-related issues

- Drive timing closure using PBA/GBA and advanced derating techniques

- Implement physical-aware timing ECOs and optimize PPA

- Perform STA vs SPICE correlation and improve signoff accuracy

- Support foundry enablement and technology node bring-up (5nm, 3nm, 2nm)

- Collaborate with cross-functional teams including P&R, CAD, and Foundry

- Develop automation using Tcl/Python for timing workflows

 AI / Automation (Preferred):

- Basic understanding of AI/LLM concepts

- Exposure to CLI-based infrastructure and automation

- Interest in intelligent workflow automation and agent-based solutions

Qualifications:

- B. Tech / M. Tech / PhD in Electrical/Electronics Engineering

- 4–6 years of experience in STA and timing closure

- Strong hands-on experience with PrimeTime and Tempus

- Solid understanding of MMMC, OCV/AOCV/SOCV, LVF

Preferred Skills:

- SPICE simulation and correlation experience

- Strong debugging skills in large SoC environments

- Python/Tcl scripting expertise

- Experience with advanced nodes and foundry interactions

Why Cadence:

- Work on industry-leading signoff tools

- Collaborate with top semiconductor and foundries

- Drive innovation in AI-enabled STA flows

- Contribute to next-generation chip tapeouts and methodology building

Behavioral skills required

• Demonstrate adaptability in a fast-paced environment, showing resilience in the face of challenges and maintaining a positive attitude.
• Exhibit a strong commitment to continuous learning and professional development, staying abreast of industry trends and technologies.
• Foster a collaborative team environment by being approachable and supportive.
• Display a proactive approach to problem-solving, taking initiative, and anticipating potential issues before they arise.

We’re doing work that matters. Help us solve what others can’t.