Overview: Before a single transistor gets placed, someone has to decide what the chip should actually be and ensure it functions to specs. This team makes those calls including System on a Chip (SoC) -level architecture, fabric/interconnect design, verification and not just core compute.

What you might work on: This posting spans multiple teams within Hardware Architecture & AI Hardware and SoC . One application, one recruiter screen - then we match you to the specific team and location that fits best. What each team does: 

• Architecture: We define and evaluate the system, CPU, memory, fabric, and chiplet-level decisions that shape future products. We analyze workloads, performance, power, and system requirements, develop architectural models, do tradeoff analyses, and specifications for implementation.
• AI Hardware: We design and develop the core AI accelerator IP, including compute, data movement, and other specialized hardware blocks that enable high-performance AI workloads. We take these IPs from requirements through RTL design, verification, and delivery for SoC integration.
• SOC : Our team is where everything comes together. We design and verify the integration of all subsystems and the final pieces that allow the chip to interact with the outside world; scaleout, memory and on-chip system management and security. We validate cross functional and performance requirements, and ultimately take the design to silicon. 

This role is on-site, based out of Boston, MA or Austin, TX or Fort Collins, CO or Santa Clara, CA. 

Who You Are

• Currently pursuing a BS, MS, or PhD in EE, ECE, CE, or CS.
• Coursework or projects in digital design, computer architecture and performance modeling.
• Self-starter who brings sound judgment and practical problem-solving to every project with a solid interest in AI and hardware, along with the ability to take ownership and deliver results.

What We Need

• Familiarity with ASIC design concepts, ranging from performance simulations, RTL design / verification,  and logic synthesis / timing analysis 
• Scripting & programming skills (example: Python, PERL, tcl, C/C++); with experience using AI coding platforms
• [Architecture] Experience with architectural simulators.
• Exposure to RISC-V or other open ISAs is nice to have.
• FPGA design experience is nice to have.

What You Will Learn

• Taking designs from specification to RTL to verification, and learning the qualification checks and tools needed to do so.
• How architectural tradeoffs (Architecture: Compute vs. memory vs. interconnect.  AI HW/ SOC: Power, Performance & Area) get decided with data, not intuition.
• Best practices for cross-functional collaboration, seeing firsthand how Architecture, RTL, Software, and Physical Design teams stay aligned through implementation.
• Practical methods to integrate AI tools directly into your daily technical workflow.
• [Architecture] Performance modeling methodology used before RTL existed.

USA Hiring Timelines

This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:

• Winter Term: Jan–Apr work term, Sept–Dec recruit.
• Summer Term: May–Aug work term, Oct–Apr recruit.
• Fall Term: Sept–Dec work term, Jan–Aug recruit.

Please note these timelines are for reference only. Actual timelines may vary.

Compensation for all interns at Tenstorrent ranges from $50/hr - $70/hr including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.