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Sobre esta vaga de Analog IC Layout Engineer na NXP Semiconductors

NXP Semiconductors · Presencial · Guadalajara

About the Team

NXP Semiconductors is seeking an Analog IC Layout Engineer to join the Central Layout Group serving the Power & Energy Business Line, with a primary focus on Automotive Power Solutions (APS).

The Central Layout Group delivers physical implementation expertise for complex mixed-signal and power management integrated circuits supporting multiple product lines worldwide. The team collaborates with Design, Verification, Package, Test and Product Engineering organizations across a global R&D network to develop next-generation automotive and industrial semiconductor solutions.

Role Summary

The successful candidate will contribute to the development of analog and mixed-signal integrated circuits, supporting physical implementation activities from block-level development through product integration. The role offers the opportunity to work within an international and multidisciplinary engineering environment.

Key Responsibilities:

Layout Development

• Develop Analog and Mixed-Signal layout blocks from schematic to tape-out
• Support floorplanning and physical implementation activities
• Optimize layouts for performance, matching, reliability and manufacturability
• Contribute to top-level integration activities

Verification and Quality

• Execute DRC, LVS, ERC and physical verification activities
• Support parasitic extraction and post-layout analysis
• Participate in design reviews and sign-off activities
• Ensure high-quality layout deliveries following NXP methodologies

Cross-Functional Collaboration

• Collaborate closely with Analog Design, Verification, Package, Test and Product Engineering teams
• Support troubleshooting and problem-solving activities during product development
• Contribute to continuous improvement of layout methodologies and best practices

Required Skills

• Bachelor or Master Degree in Electrical Engineering, Electronics, Physics or Microelectronics
• Knowledge of Analog IC Layout methodologies
• Experience with Cadence Virtuoso Layout environment
• Understanding of DRC/LVS verification concepts
• Familiarity with Linux working environments
• Strong analytical and problem-solving skills
• Ability to collaborate effectively in multicultural and international teams
• Fluent written and spoken English

Preferred Qualifications

• Experience with Calibre, PVS or equivalent verification tools
• Knowledge of CMOS, BCD or High Voltage technologies
• Knowledge of Analog Mixed-Signal integrated circuits
• Basic scripting skills (SKILL, Python, TCL or Shell)
• Experience in automotive semiconductor development
• Interest in layout automation and methodology improvements

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Thank you for your interest in supporting our recruitment efforts. Please note that NXP operates under a strict Preferred Supplier List (PSL) for all recruitment activities. Any candidate profiles or resume submitted without a prior written agreement or explicit request from our Talent Acquisition team will be considered unsolicited. Such submissions will be deemed free of any obligations, and no fees will be paid by NXP or any of its affiliates, subsidiaries, or divisions - regardless of whether the candidate is hired, either coincidentally or otherwise. Thank you for your understanding.

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