Tenstorrent is seeking an experienced Field Application Engineer to champion our revolutionary RISC-V CPU and AI accelerator IP products with customers worldwide. You will own end-to-end technical engagements, translating complex architectural advantages into customer wins while shaping our product roadmap through direct market feedback. If you combine deep technical expertise with exceptional customer engagement skills and want to drive the adoption of next-generation compute IP, join our team.

This role is hybrid, based out of the United States or Canada near one of our main office locations.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A customer-focused engineer with proven success in CPU/GPU/NPU IP sales engagements.
• Technical expert who can articulate complex architectural benefits and conduct deep-dive analyses.
• Self-driven professional who independently manages multiple customer relationships from discovery to win.
• Strategic thinker who identifies customer pain points and positions solutions effectively.

What We Need

• 7+ years in the semiconductor industry with a degree in EE or related field including customer-facing roles in CPU IP.
• Hands-on expertise with ASIC design flows, IP integration, and relevant design views (.lib, LEF, ICL, PDL).
• Deep technical knowledge of CPU architectures, semiconductor technologies, and system-level design.
• Exceptional presentation and communication skills with ability to engage all organizational levels.
• Proven track record of technical wins and managing multiple simultaneous accounts.

What You Will Learn

• How to position cutting-edge RISC-V and AI accelerator IP against industry incumbents.
• Advanced customer engagement strategies for complex technical sales in the semiconductor industry.
• Direct influence on product development through customer feedback and market insights.
• The complete IP business cycle from evaluation through design win and production success.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Tenstorrent is seeking an AI Processor IP Product Engineer to be the technical bridge between our cutting-edge AI processor technology and customer success. You'll guide customers through the integration of our advanced AI processors, RISC-V CPUs, and chiplet solutions into their SoCs, ensuring optimal performance and accelerated time-to-market. If you thrive in customer-facing roles and want to shape the deployment of revolutionary AI hardware across the industry, join our team.

This role is hybrid, based out of Toronto, Canada or Vancouver, Canada.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A customer-focused engineer with deep technical expertise in ASIC design and IP integration.
• Experienced problem-solver who excels at debugging complex system-level issues and silicon bring-up.
• Strong communicator who builds trusted relationships while managing technical engagements across the support lifecycle.
• Passionate about enabling customer success and translating complex technical concepts into actionable guidance.

What We Need

• 3-5 years in the semiconductor industry with a degree in EE or related field.
• Hands-on expertise with ASIC design flows, IP integration, and relevant design views (.lib, LEF, ICL, PDL).
• Strong background in analog/digital design tools, silicon validation, and system-level debug.
• Proven track record in customer-facing engineering roles with excellent communication skills.

What You Will Learn

• How to integrate state-of-the-art AI processors and chiplet architectures into diverse customer SoCs.
• Advanced debugging techniques spanning pre-silicon simulation to post-silicon validation.
• Strategies for influencing product roadmaps through direct customer feedback and technical insights.
• The full spectrum of IP productization—from technical documentation to customer training and support processes.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

About The Team 

Cerebras builds wafer-scale AI processors—single chips delivering tens of PB/s of memory bandwidth and a dataflow architecture that accelerates at a granularity no multi-device system can match. The Advanced Technology Group (ATG) is Cerebras’ pathfinding organization. We work ahead of product to explore new architectures, demonstrate breakthrough performance on scientific and AI workloads, and shape the technical roadmap for future Cerebras hardware and software. Our work regularly appears at top-tier venues (Supercomputing, SIAM, IEEE, and NeurIPS) and directly influences the design of next-generation wafer-scale systems. 

About The Role 

Most AI research today is shaped by the constraints of existing hardware. This role starts from the other direction: what would you build if the architecture let you rethink the fundamentals? You will design and develop AI models and training methodologies on wafer-scale hardware, working at the level of optimization theory, model architecture, and statistical foundations rather than assembling existing components. 

The ATG sits at the intersection of AI, computational science, and computer architecture, and your work will draw on all three. You will collaborate closely with Cerebras’ ASIC, compiler, kernel, and AI teams as well as external partners at universities and national laboratories. 

What You Will Do 

• Design AI models and training methods from first principles, leveraging architectural properties of wafer-scale hardware that are unavailable on conventional platforms. 
• Investigate how techniques from computational science—numerical methods, PDE solvers, simulation—can inform and advance AI model design, and explore hybrid workflows that couple simulation and learning. 
• Develop a deep understanding of the hardware substrate and use it to guide algorithmic choices: model structure, optimization strategy, memory access patterns, numerical precision. 
• Publish findings and present at top-tier venues (NeurIPS, ICML, ICLR, etc.); represent Cerebras in the broader AI/ML research community. 
• Inform the design of future Cerebras hardware and software by identifying the computational patterns that matter most for next-generation AI workloads. 

What We Are Looking For 

• PhD in Machine Learning, Computer Science, Applied Mathematics, Statistics, Physics, or a related quantitative field preferred; exceptional candidates without a graduate degree who demonstrate equivalent depth through published research, significant open-source contributions, or a strong industry track record are encouraged to apply. 
• Mathematical maturity: comfort with the theory behind gradient methods, loss landscapes, generalization, and the relationship between model structure and data statistics. 
• Track record of published research at top-tier AI or computational science venues. 
• Proficiency in Python and PyTorch; comfort with C or other low-level languages is a strong signal. 
• Excellent communication and interpersonal skills: able to present complex technical material to both ML and systems audiences, and to collaborate effectively in a fast-paced, small-team environment. 

Why This Opportunity Is Exciting And Unique 

• You will have direct access to hardware that changes what’s algorithmically possible. Tens of PB/s of memory bandwidth and fine-grained dataflow execution open design spaces that don’t exist on GPU clusters. 
• You will work alongside researchers in computational science, computer architecture, and performance engineering. The synthesis across these fields is central to ATG’s approach. 
• Your research will influence silicon - ATG’s findings directly shape the design of future Cerebras chips and systems. 

We are hiring for multiple positions across experience levels. If this work resonates, we encourage you to apply. 

About The Team 

Cerebras builds wafer-scale AI processors—single chips delivering tens of PB/s of memory bandwidth and a dataflow architecture that accelerates at a granularity no multi-device system can match. The Advanced Technology Group (ATG) is Cerebras’ pathfinding organization. We work ahead of product to explore new architectures, demonstrate breakthrough performance on scientific and AI workloads, and shape the technical roadmap for future Cerebras hardware and software. Our work regularly appears at top-tier venues (Supercomputing, SIAM, IEEE, and NeurIPS) and directly influences the design of next-generation wafer-scale systems. 

About The Role 

We are seeking Compiler Engineers to join a small team of specialists working on our emerging Tungsten language compiler. Tungsten is Cerebras’ dataflow programming language, purpose-built for wafer-scale hardware. You will work on the Tungsten compiler from language design through code generation, building the toolchain that translates high-level intent into efficient execution across hundreds of thousands of cores with a memory and interconnect model unlike anything in conventional computing. 

This is not incremental work on an existing backend. The architecture is new, the programming model is new, and the compiler is where those two things meet. You will collaborate closely with Cerebras’ ASIC, kernel, and AI teams, and your design decisions will directly shape both the language and the hardware it targets. Beyond the compiler itself, the broader toolchain—runtime, debugger, simulator—is still being built, and we are equally interested in engineers who want to own those pieces of the developer experience on novel hardware. 

What You Will Do 

• Design and implement compiler passes across the Tungsten toolchain: mid-end optimization, backend code generation, instruction scheduling, register allocation, assembler, and linker. 
• Co-design language constructs that improve expressiveness and performance for dataflow execution on wafer-scale hardware. 
• Develop and iterate on code generation strategies for complex scientific and AI workloads, analyzing performance bottlenecks and closing the gap between peak and achieved throughput. 
• Extend the compiler to support future hardware architectures as they move from design to silicon. 
• Work directly with ASIC architects and application researchers to inform hardware-software co-design decisions. 

What We Are Looking For

• PhD in Computer Science or Computer Engineering preferred; exceptional candidates without a graduate degree who demonstrate equivalent depth through published research, significant open-source contributions, or a strong industry track record are encouraged to apply. 
• Substantial experience in compiler development: IR design, optimization passes, code generation, or backend implementation for novel or non-standard architectures. 
• Strong grasp of computer architecture: instruction sets, memory models, dataflow execution, and how hardware constraints shape compilation strategy. 
• Systems-level programming ability in C; comfort reasoning about performance at the instruction and memory-access level. 
• Ability to think about compilation as a design problem, not just an implementation task: you should have opinions about how language semantics, compiler IR, and hardware capabilities interact. 
• Excellent communication and interpersonal skills: able to work effectively in a small, fast-moving team where compiler, architecture, and application concerns are deeply intertwined. 

Valuable Assets 

• Experience with compilers for spatial, dataflow, or CGRA architectures where the compilation model diverges significantly from conventional CPU/GPU targets. 
• Exposure to ML compiler frameworks (MLIR, XLA, TVM) and understanding of how AI workloads map to hardware. 
• Experience with multi-dimensional data representations, tiling strategies, and vectorized operations. 
• Track record of published research or patents in compilers, programming languages, or architecture. 
• Experience building runtime systems, debuggers, or architecture simulators, particularly for non-standard hardware. 
• Understanding of parallel/distributed systems and cluster computing. 

Why This Opportunity Is Exciting And Unique 

• Build a compiler for hardware that doesn’t exist anywhere else. The architecture is the constraint and the opportunity. 
• Publish and open-source your research. We present at Supercomputing, SIAM, IEEE, NeurIPS, and beyond. 
• Work on the fastest AI system in the world, with direct access to the hardware your compiler targets. 
• Join at a pivotal moment: Cerebras is pre-IPO with strong commercial traction and rapid growth. 
• Be part of a small, technical team with high autonomy, minimal bureaucracy, and a culture that values depth over hierarchy. 

We are hiring for multiple positions across experience levels. If this work resonates, we encourage you to apply. 

About The Team 

Cerebras builds wafer-scale AI processors—single chips delivering tens of PB/s of memory bandwidth and a dataflow architecture that accelerates at a granularity no multi-device system can match. The Advanced Technology Group (ATG) is Cerebras’ pathfinding organization. We work ahead of product to explore new architectures, demonstrate breakthrough performance on scientific and AI workloads, and shape the technical roadmap for future Cerebras hardware and software. Our work regularly appears at top-tier venues (Supercomputing, SIAM, IEEE, and NeurIPS) and directly influences the design of next-generation wafer-scale systems. 

About The Role 

We are seeking R&D Engineers to join Cerebras' Advanced Technology Group. You will design and implement workloads that establish new performance benchmarks on wafer-scale hardware, leveraging architectural features that no traditional platform offers. The 
scope ranges from large-scale scientific simulations to emerging AI/ML models, and the work sits at the intersection of algorithm design, compiler co-optimization, and hardware architecture. You will collaborate closely with Cerebras’ ASIC, compiler, kernel, and AI teams as well as external partners at universities and national laboratories. 

What You Will Do 

• Design and implement challenging scientific computing and AI workloads on Cerebras’ Wafer-Scale Engine, targeting performance results that advance the state of the art. 
• Lead algorithm–hardware co-design efforts with internal R&D teams and external research partners, turning architectural capabilities into measurable application-level advantages. 
• Build analytical performance models that quantify bottlenecks, guide optimization, and inform future chip and compiler design decisions. 
• Contribute to Cerebras’ multi-year technology roadmap by identifying high-impact workloads, proposing architectural experiments, and validating them on silicon. 
• Publish findings and present at top-tier conferences and journals; represent Cerebras in the broader HPC and AI research communities. 

What We Are Looking For 

• PhD in Computer Science, Engineering, Applied Mathematics, Physics, or a related quantitative field preferred. Exceptional candidates without a graduate degree who demonstrate equivalent depth through published research, significant open-source contributions, or a strong industry track record are encouraged to apply. 
• Deep experience in at least one of the following: computer architecture and accelerator design; parallel, distributed, or high-performance computing; numerical methods and scientific simulation; AI/ML theory and model design at a mathematical level. 
• Strong ability to analytically model and optimize the performance of complex systems and algorithms. 
• Track record of published research or patents in relevant venues. 
• Proficiency in C and Python; comfort working close to hardware. 
• Excellent communication and interpersonal skills: able to present complex technical material to both specialist and cross-functional audiences, and to collaborate effectively in a fast-paced, small-team environment. 

Areas Of Particular Interest 

We are hiring across several focus areas. Exceptional depth in one or more of the following is a strong signal: 

• Computational science: researchers who can bring insights from numerical methods and simulation into AI, or couple simulation and learning into joint computational workflows. Depth in hydrodynamics, solid mechanics, electromagnetics, molecular dynamics, or related PDE-based fields. 
• AI/ML foundations: deep understanding of model architecture, optimization methods, and their statistical underpinnings—the ability to design from first principles, not just apply established recipes. 
• Computer architecture: microarchitecture design, computing paradigms at the circuit and datapath level, memory hierarchy design. 
• Performance engineering: roofline modeling, bandwidth analysis, kernel optimization, communication-computation overlap, and compiler-level tuning for novel hardware. 

Why This Opportunity Is Exciting And Unique 

• Build on a fundamentally different architecture, unconstrained by GPU assumptions. 
• Publish and open-source your research. We present at Supercomputing, SIAM, IEEE, NeurIPS, and beyond. 
• Work on the fastest AI system in the world, with direct access to the hardware your compiler targets. 
• Join at a pivotal moment: Cerebras is pre-IPO with strong commercial traction and rapid growth. 
• Be part of a small, technical team with high autonomy, minimal bureaucracy, and a culture that values depth over hierarchy. 

We are hiring for multiple positions across experience levels. If this work resonates, we encourage you to apply.