PsiQuantum’s mission is to build the first useful quantum computers—machines capable of delivering the breakthroughs the field has long promised. Since our founding in 2016, our singular focus has been to build and deploy million-qubit, fault-tolerant quantum systems. 

Quantum computers harness the laws of quantum mechanics to solve problems that even the most advanced supercomputers or AI systems will never reach. Their impact will span energy, pharmaceuticals, finance, agriculture, transportation, materials, and other foundational industries. 

Our architecture and approach is based on silicon photonics. By leveraging the advanced semiconductor manufacturing industry—including partners like GlobalFoundries—we use the same high-volume processes that already produce billions of chips for telecom and consumer electronics. Photonics offers natural advantages for scale: photons don’t feel heat, are immune to electromagnetic interference, and integrate with existing cryogenic cooling and standard fiber-optic infrastructure. 

In 2024, PsiQuantum announced government-funded projects to support the build-out of our first utility-scale quantum computers in Brisbane, Australia, and Chicago, Illinois. These initiatives reflect a growing recognition that quantum computing will be strategically and economically defining—and that now is the time to scale. 

PsiQuantum also develops the algorithms and software needed to make these systems commercially valuable. Our application, software, and industry teams work directly with leading Fortune 500 companies—including Lockheed Martin, Mercedes-Benz, Boehringer Ingelheim, and Mitsubishi Chemical—to prepare quantum solutions for real-world impact. 

Quantum computing is not an extension of classical computing. It represents a fundamental shift—and a path to mastering challenges that cannot be solved any other way. The potential is enormous, and we have a clear path to make it real. 

Come join us. 

Job Summary:

PsiQuantum is seeking a Quantum Electronics Engineer to support the development of advanced electronic and electro-optic systems for quantum computing.

In this role, you will work closely with senior engineers to design and implement high-performance electronic solutions for controlling and reading out quantum photonic hardware. This includes RF design, electro-optic modulation, and low-latency control systems.

Responsibilities:

• Design and develop RF and high-speed electronic systems for quantum hardware applications.
• Support the design of electro-optic (EO) packages and modulator driving electronics.
• Develop low-latency electronic solutions for quantum system control and readout.
• Work on readout systems for superconducting nanowire single-photon detectors (SNSPDs).
• Collaborate with photonics and quantum teams to integrate electronics with optical systems.
• Assist in FPGA-based system design and implementation for control and data acquisition.
• Participate in debugging and optimization of complex quantum hardware systems.

Experience/Qualifications:

• Degree (PhD or equivalent experience) in Electrical Engineering, Physics, or a related field.
• Strong background in RF and high-speed electronic design.
• Experience working with electro-optic systems or photonic hardware.
• Understanding of signal integrity, noise, and timing in high-performance systems.
• Hands-on laboratory experience with electronic test and measurement equipment.

Desired Skills:

• Experience designing electronics for quantum or cryogenic systems.
• Familiarity with FPGA development and programming.
• Knowledge of superconducting nanowire detectors and readout electronics.
• Experience with low-latency system design and high-speed data acquisition.
• Experience with ASIC design or collaboration with ASIC development teams for high-speed or low-latency electronic systems.

PsiQuantum provides equal employment opportunity for all applicants and employees. PsiQuantum does not unlawfully discriminate on the basis of race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, gender expression, national origin, ancestry, citizenship, age, physical or mental disability, military or veteran status, marital status, domestic partner status, sexual orientation, genetic information, or any other basis protected by applicable laws.

Note: PsiQuantum will only reach out to you using an official PsiQuantum email address and will never ask you for bank account information as part of the interview process. Please report any suspicious activity to recruiting@psiquantum.com.

We are not accepting unsolicited resumes from employment agencies.

Position Overview

We are seeking a SoC Validation Engineer.

The Silicon Team in Edinburgh is a small, highly focused group responsible for developing high‑value silicon that is core to AST’s mission of “Connecting the unconnected”—delivering the world’s first space‑based mobile broadband network.

The team works collaboratively to define and build next‑generation silicon, exploring advanced silicon technologies to continuously improve performance, capability, and efficiency. This is a hands‑on environment where silicon decisions directly impact AST’s ability to deliver a global communications network from space.

In this role, the Validation Engineer will be responsible for defining, executing, and reporting on the validation of complex integrated circuit devices, working closely with System Definition, IC Design, and Software teams. This role spans pre‑silicon validation using FPGA prototypes through to post‑silicon bring‑up and system‑level validation, ensuring devices meet performance, functionality, and system integration requirements.

Key Responsibilities:

• Work closely with System Definition and IC Design teams to ensure devices are specified with optimal ball placement and external component selection to meet PCB technology and overall system requirements.
• Define and specify laboratory equipment and infrastructure required to effectively test and validate devices.
• Perform validation bring‑up using FPGA prototypes prior to IC manufacture.
• Define comprehensive validation test plans to validate IC performance either standalone or within a wider system, covering hardware, software, and RF aspects.
• Execute manual bring‑up and planned validation test activities, including fault isolation and debug.
• Define, develop, and implement regression and automation procedures to improve validation efficiency and coverage.
• Produce clear and concise validation reports for technical review and sign‑off.
• Support board‑level bring‑up and debug activities in collaboration with hardware and software teams.

Qualifications

Education:

BEng in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.

Experience:

• Minimum of 4+ years of relevant industry experience.
• Hands‑on experience using laboratory equipment including spectrum analyzers, oscilloscopes, signal generators, network analyzers, and similar instrumentation.
• Practical experience with scripting or programming languages such as Python, Perl, C, or C++.
• Strong verbal communication and technical documentation skills.
• Experience working effectively across multidisciplinary teams.

Preferred Qualifications:

• Experience with DSP, wireless communication systems, and SerDes technologies.
• Experience validating complex System‑on‑Chip (SoC) designs involving embedded software.
• Background knowledge of RF fundamentals, antennas, and communication theory.

Soft Skills:

• Strong verbal communication skills.
• Strong technical documentation skills.
• Ability to work effectively across multidisciplinary teams.
• Ability to collaborate closely with System Definition, IC Design, Software, hardware, and validation teams.

Technology Stack:

• Laboratory validation equipment (spectrum analyzers, oscilloscopes, signal generators, network analyzers).
• FPGA prototypes for pre‑silicon validation.
• Python, Perl, C, C++.

Physical Requirements

• Ability to work in a standard office and laboratory environment and use a computer for extended periods.
• Occasional travel may be required to visit suppliers, partners, or other AST SpaceMobile design centres.

This job description may not be inclusive to the duties and responsibilities listed. Additional tasks may be assigned to the employee from time to time or the scope of the job may change as needed by business demands. 

Hudson River Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset to join our growing Hardware team. In this role, you will help deliver performance-critical ASICs and advance our physical design methodologies on leading-edge process nodes.

The Hardware team at HRT builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions on global markets. We create custom solutions across the full spectrum of speed and sophistication, from bespoke circuits to world-class machine learning accelerators.

Responsibilities

• Drive design-for-test (DFT) methodologies and implementation 
• Contribute to physical implementation, from RTL handoff through GDSII on advanced process nodes 
• Partner on floorplanning and physical optimization for high-performance, latency-critical designs
• Close timing across multiple modes and corners while optimizing power, performance, and area (PPA)
• Diagnose and resolve physical design issues such as timing bottlenecks, congestion, and IR/EM violations
• Build, maintain, and improve repeatable, automated physical design flows
• Develop scripts and tooling to improve productivity, robustness, and insight into design behavior
• Collaborate closely with RTL, architecture, and other hardware engineers to influence design decisions early

Qualifications

• Experience working in high-performance ASIC design environments
• Strong fundamentals in digital logic, circuit design, and process technology
• Familiarity with DFT concepts and testing methodologies
• Strong scripting and automation skills (Python, Tcl, shell), including parsing and analyzing tool outputs
• Ability to design robust methodologies, diagnose complex failures, and improve physical design flows
• Applied use of statistics in analyzing timing, power, or design data (preferred)
• Hands-on experience with static timing analysis and timing closure methodologies
• Expertise using industry-standard physical design and signoff tools (e.g., Innovus, PrimeTime)

This job is accepting ongoing applications and there is no application deadline.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Hudson River Trading (HRT) is hiring an AI Researcher to join the HAIL team. HAIL (HRT AI Labs) is the team at HRT responsible for developing and maintaining our most powerful models, which are used by our trading teams to drive a significant fraction of our trading. We are building and deploying "foundation models for markets", that ingest and train on vast amounts of market data, to make predictions about future market state. We are seeking experienced AI researchers to join our team to accelerate our efforts.

Researchers have great independence to pursue the research directions they think would be most impactful as part of a small focused team with minimal bureaucracy. They are enabled by state-of-the-art research clusters with very high GPU-to-researcher ratios, and supported by excellent engineering, hardware, and systems teams to realize their vision. Your work will be directly, clearly, highly impactful on the business, and it will be challenging: this is a field with no easy or obvious solutions. You'll be responsible for improving every part of our models: from featurization of data, to architecture design, to training dynamics, to how trading decisions are made.

Qualifications

• Must have two or more years work experience in deep learning research, for any domain: robotics, biology, chemistry, physics, audio, video, etc.
• Experience translating methods between areas of application is highly valued.
• LLM experience is valuable, but not necessary.
• Strong engineering skills valued, especially any of: GPU kernel development, lower-level Pytorch/JAX development, intermediate C++, FPGA/ASIC experience, HPC experience.

The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. 

This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company’s retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Writing detailed verification plans
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications 

• Superb debug and analytical skills 
• Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with SystemVerilog and industry-standard frameworks such as UVM
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

About the Position

We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you’ll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.

We’re big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That’s why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don’t expect you to know OCaml (we’ll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You

• Have 4+ years practical experience in RTL design and verification
• Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following:
  
  • Front-end RTL design and synthesis
  • Back-end physical design
  • Verification (including formal)
• Interested in using software engineering techniques to improve the hardware design process, and experience programming in some high-level languages (Python, C++, Java, Haskell, etc.)
• Fluent in English 

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com. 

About the Position

We are looking to hire an Engineer with experience in both software and hardware design to help us build our FPGA-based applications. 

We're big believers in the ability of tools to make programming faster, more pleasant, and more reliable. We apply these same principles to our FPGA Engineering work, and we’re looking for people who are interested in using programming language technology to improve the process of designing, testing, and validating hardware designs. We use Hardcaml, an OCaml library for succinctly describing hardware in RTL. Hardcaml is tightly integrated into our development environment, so you’ll also gain lots of exposure to the libraries and tools that are foundational to our internal systems. No previous knowledge of Hardcaml is required.

In this role, you’ll work on the ground-up design and implementation of new FPGA applications, and help extend and refine the high-level design and testing tools that we use internally. Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing/integration, but you can also expect to work with some Verilog and C. While you don’t need to have worked with OCaml specifically, a good background in typed programming languages is a plus.

If you’d like to learn more, you can read about our interview process, meet some of our newest hires, or check out our OCaml All The Way Down talk and Programmable Hardware podcast episode.

About You

We don’t expect you to have a background in OCaml, finance, or any other specific field—we’re looking for smart programmers who will approach hardware design with a software engineering mindset. We’re more interested in how you think and learn than what you currently know. You should be:

• A top-notch programmer with a love for technology
• Comfortable with a software programming language
• Intellectually curious, collaborative, and eager to learn
• Humble and unafraid to ask questions and admit mistakes
• Experienced with a Hardware Description (or Construction) language (VHDL, Verilog, Chisel, Pymtl, or other), for both writing and testing hardware designs
• Experienced working with FPGA vendor tools (Vivado or Quartus)
• Experienced with building a working FPGA project through an academic, professional, or personal project
• Interested in learning how to use FPGAs in the context of networking
• Fluent in English

If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.

We are looking for a Telecommunication Ground Station Engineer to design, deploy, and maintain satellite communication infrastructure across our global network. You’ll work on radio interfaces, signal processing pipelines, and satellite tracking systems ensuring reliable uplink/downlink with our spacecraft. This role offers hands-on development across software, hardware, and RF layers.

Your responsibilities will include:

• Develop and maintain automated ground stations for satellite telemetry, tracking, and control (TT&C).
• Configure radio interfaces (UHF/VHF/S/X-band), modems for telemetry, telecommand and data downlink and uplink.
• Work with software-defined radios for dynamic communication tasks.
• Test, validate, maintain and monitor radio frequency antenna system such as LNA, LNB, filters and more.
• Design, test, and integrate antenna rotator controllers for auto-tracking satellites.
• Deploy and manage ground station software.
• Build scalable data routing systems for real-time and store-and-forward communication using cloud APIs.
• Coordinate with the avionics and mission ops teams for satellite pass predictions and data ingestion.
• Develop dashboards for real-time telemetry visualization.

Qualifications

We’re looking for Telecommunication Engineer with solid technical fundamentals and the drive to learn quickly working across architecture, implementation and troubleshooting with strong ownership and problem-solving mindset.

Required

• Bachelor’s degree or Master’s degree in Electronics, Telecommunications, Aerospace, or related field.
• 2–5 years of experience in ground station operations, RF communication, or satellite systems.
• Hands-on experience with radio hardware.
• Proficient in C++, Python, Linux, scripting, and working with serial/UART, TCP/IP interfaces.
• Solid understanding of link budgets, Doppler shift compensation, and signal modulation.
• Experience in RF antenna design and concepts.

Nice to have

• Exposure to embedded system development (Xilinx FPGA, DMA, ARM architecture, PS/PL)
• Experience with space communication standards such as ETSI DVB-S2X or CCSDS TM/TC/SCCC

About the Role

• Spire operates a hybrid work model, and this position will require you to work a minimum of three days per week in the office.
• Access to US export-controlled software and/or technology may be required for this role. If needed, Spire will arrange the necessary licenses—this is not something candidates need to have before applying. #LI-RK1

We are looking for a Spacecraft Software Engineer (GNSS) to join our team working at the intersection of satellite payloads, scientific computing, and data delivery systems. In this role, you'll be responsible for developing and maintaining both the flight and ground software that powers our satellite-based GNSS missions. You’ll work across system layers—from embedded software to cloud data pipelines—to help ensure the accurate and timely delivery of mission-critical scientific data to our customers.   

This is a high-impact role where autonomy, creativity, and technical breadth are key.   

What You'll Do as a Senior Software Engineer:

• Develop and maintain scientific and command & control software for GNSS-based satellite payloads using a variety of software stacks.   

• Build and operate ground-based automation systems for efficient data extraction, transformation, and delivery from the satellite to end users.   

• Collaborate closely with flight operations to troubleshoot and ensure consistent, high-quality data delivery.   

• Engage with other system engineers, payload developers, and mission operators to continuously evolve the software in support of scientific objectives.   
• Participate in code reviews, testing, and documentation to uphold software reliability and traceability.   

Who You Are (Required Qualifications):

We're looking for someone with at least 5 of the following qualifications:   

• Proficient in at least one of C++ or Python, and capable of picking up new tools and languages as needed.   

• Experience in FPGA development (VHDL or HLS) for signal processing or control systems.   

• Solid background in DSP techniques and theory, especially in the context of RF or GNSS.   

• Familiarity with GNSS signal processing and/or scientific applications such as GNSS-RO, GNSS-R, or PNT algorithms.   

• Skilled in cloud-based systems (e.g., AWS), backend development, and managing data via scalable storage/database solutions.   

• A lifelong learner—curious, adaptable, and open to new challenges outside your immediate expertise.   

• Demonstrates strong work ethics and a focus on impactful contributions to the mission and team.   

• Capable of independently navigating technical challenges and making forward progress without constant direction.   

Preferred Skills:

• Prior experience working on satellite payloads or in the aerospace domain.   

• Experience building telemetry and data visualization tools.   

• Contribution to open-source scientific or aerospace-related software projects. 

Spire operates a hybrid work model, and this position will require you to work a minimum of three days per week in the office.

Access to US export-controlled software and/or technology may be required for this role. If needed, Spire will arrange the necessary licenses—this is not something candidates need to have before applying. #LI-RK1