DRW is a diversified trading firm with over 3 decades of experience bringing sophisticated technology and exceptional people together to operate in markets around the world.  We value autonomy and the ability to quickly pivot to capture opportunities, so we operate using our own capital and trading at our own risk. 

Headquartered in Chicago with offices throughout the U.S., Canada, Europe, and Asia, we trade a variety of asset classes including Fixed Income, ETFs, Equities, FX, Commodities and Energy across all major global markets. We have also leveraged our expertise and technology to expand into three non-traditional strategies: real estate, venture capital and cryptoassets. 

We operate with respect, curiosity and open minds. The people who thrive here share our belief that it’s not just what we do that matters–it's how we do it.  DRW is a place of high expectations, integrity, innovation and a willingness to challenge consensus.  

We are currently seeking a Senior FPGA Engineer to join one of our trading teams. While DRW has been leveraging FPGA technology for a number of years, you will have the opportunity to build an FPGA application from scratch for an existing team. We’re seeking a candidate that has a strong understanding of software and hardware interaction. This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design.

Responsibilities: 

• Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
• Research and evaluate a variety of cutting-edge FPGA hardware and technologies
• Propose creative solutions to overcome FPGA/hardware limitations
• Liaise directly with software and other design teams
• Conduct lab debugging and characterization of new hardware

Candidate Requirements:

• Bachelor's degree or higher, Computer/Electrical Engineering graduated with honors from a leading university,  with 3+ years of experience within the field; (Master's degree or higher also counts for experience)
• Solid Hardware Engineering experience, especially with FPGA
• Highly autonomous with a can-do attitude able to lead an FPGA based project from system requirements to production
• Strong capacity to quickly evaluate FPGA based project feasibility based on hardware limitation
• Strong skills in RTL logic design and verification; 2+ years of experience writing Verilog or SystemVerilog
• Strong knowledge of FPGAs fabric
• Experience in FPGA design flow including synthesis, place & route, static timing analysis is required
• Knowledge of Ethernet and Gigabit high speed serial interfaces
• Strong working knowledge of either XILINX or ALTERA FPGA design flow
• Experience with Python verification framework is a plus
• Excellent research and data gathering skills
  
  

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Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• Physical Implementation & Execution

  • Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
  • Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
  • Own macro-level implementation with deep hands-on experience in floorplanning and complex routing

• Signoff & Design Integrity

  • Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
  • Ensure first-pass silicon success through rigorous signoff flows and analysis
  • Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness

• Methodology Development & Cross-Functional Collaboration

  • Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
  • Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
  • Leverage scripting and automation to make engineering environment faster and more robust

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related technical field
• 3+ years of hands-on experience in Physical Design at semiconductor companies
• Proven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing
• Experience working with advanced process technologies (7nm and below)
• Solid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis
• Proficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks

Preferred Qualifications

• Experience with full-chip level implementation and integration
• Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon
• Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout
• Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
• Background in high-speed interface designs or connectivity protocols

Simply’s mission is to make the pursuit of creative hobbies simple and fun. Our top-grossing apps Simply Piano, Simply Guitar, Simply Sing, and Simply Draw put us on the fast track to building the world’s largest global consumer subscription service that’s revolutionizing how we spend our time at home. With over a million monthly downloads and hundreds of thousands of daily learners around the world, we’re redefining creative learning at scale.

What Senior AI Research Engineers do at Simply

Senior AI Research Engineers at Simply develop algorithmic solutions that power new innovative features and continuously improve existing ones, with a strong emphasis on training AI / ML models as a core part of the role. The work spans a wide range of domains - from training generative AI and LLM-based models to create musical content at scale for Simply Piano, through building deep learning computer vision models that enhance user drawings in Simply Draw, to developing real-time audio ML models for music transcription that elevate feedback in Simply Guitar. 

You will take full end-to-end ownership of cutting-edge algorithms and AI models - leading the process from ideation and research, through development, to production-grade implementation and engineering within Simply’s products. This includes not only designing and building AI models, but also ensuring robust, efficient, and scalable integration into the app - directly shaping the experience of millions of users.

Who you are and what you’ve done

• Master's degree in Electrical Engineering, Computer Science, Physics, or a related field
• 3+ years of experience in designing and implementing AI/ML algorithms, with a strong focus on signal processing
• Proven experience working across the full ML lifecycle - from data acquisition and model training to production implementation and ongoing product iteration.
• Moves fast, with strong engineering instincts, able to choose the right level of complexity to drive real-world impact
• A get things done attitude with a strong sense of ownership
• A team player with excellent communication and collaboration skills; able to convey complex ideas clearly to technical and non-technical partners
• Exceptional analytical and problem-solving skills
• A fast learner, willing to try things out of your comfort zone
• Experience in speech, audio, or music-related domains - Advantage

We are looking for a highly motivated Senior Software and Algorithm Engineer to join our team!

As a Senior Software and Algorithm Engineer you will help us with implementing innovative bioinformatics algorithms and extracting more insights from the data our product generates.

How You’ll Contribute

• Participate in the architecture and software design of bioinformatics solutions
• Implement bioinformatic algorithms in an efficient, reusable and manageable C/C++ code
• Learn in-depth the required algorithms, analyze their complexity and find/invent ways to implement them in the most efficient way possible
• Work on existing and on new pipeline infrastructures, both on-prem and at cloud environments
• Manage performance tuning, integrations, testing and bug fixing

Qualifications, Skills, Knowledge & Abilities

• BS degree in Electrical Engineering, Software Engineering, Computer Science or equivalent
• MS degree or other advanced studies in above fields is a plus
• 5+ years of experience working as a senior software engineer
• 5+ years of experience working with C/C++
• Experience in implementing analytical algorithms in C/C++, similar language or lower-level code.
• Experience with bioinformatics algorithms is a plus
• Familiarity with other programing languages: Python, Java, R, Rust
• Familiarity with public cloud environments (AWS, GCP, Azure), Containers (docker) and Orchestrators (K8S)
• Knowledge of workflow management systems (e.g., Prefect, Airflow, Luigi)
• Familiarity with pipeline languages such as WDL, Nextflow or Snakemake is a plus#L

#LI-Hybrid