We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. This is a CPU tech-leadership role focused on driving power analysis and projections for the development of CPU chiplet with an emphasis on power analysis. The role involves defining CPUrail planning while collaborating closely with SoC and Board teams. Responsibilities include optimizing the system PDN for Block rails, and managing the power vector plan for comprehensive coverage of Chip level. The position requires driving power analysis on RTL and Netlist using tools like Joules and PrimePower, working with RTL design, synthesis, and physical design teams to measure and optimize power, and evaluating new power optimization techniques at various design stages. Additionally, the role involves tabulating metrics results for analysis comparison and workingwith post-silicon teams to correlate projections with silicon power measurements.

This role is hybrid, based out of Tokyo, Japan

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Extensive experience in power analysis and optimization for complex ASICs (typically 10+ years of ASIC or related design experience).
• Comfortable working across RTL, synthesis, and physical design stages, including low‑power implementation techniques and ECO‑based timing closure.
• Proficient with power analysis tools (e.g., Joules, PrimePower) and scripting (Tcl plus at least one of Python or similar).
• Strong analytical and problem‑solving skills, with clear written and verbal communication when collaborating across SoC, board, and post‑silicon teams.
• Nice to have: familiarity with UPF/CPF low‑power intent, Verilog/SystemVerilog, CPU micro‑architecture and its power challenges, and basic thermal analysis.

What We Need

• Own power analysis and projections for the CPU chiplet, with emphasis on defining and tracking power metrics throughout the design cycle.
• Define and maintain the power vector plan for comprehensive chiplet‑level and chip‑level coverage.
• Drive power analysis on RTL and netlist using tools such as Joules and PrimePower, partnering with RTL design, synthesis, and physical design teams to measure and optimize power.
• Evaluate and propose new power optimization techniques at RTL, synthesis, and physical design stages, and implement changes via timing ECO and flow updates.
• Tabulate and compare power metrics and reports across design iterations, and work with post‑silicon teams to correlate projections with silicon measurements.

What You Will Learn

• How to define and execute a power strategy for a 2nm CPU chiplet within a multi‑chiplet system‑in‑package, including rail planning and system‑level PDN optimization.
• Best practices for end‑to‑end power closure, from RTL through netlist and physical design, in collaboration with global RTL, SoC, and board teams.
• How to correlate pre‑silicon power models with real silicon behavior and feed lessons learned back into next‑generation CPU and SiP architectures.
• How Tenstorrent integrates CPU chiplets, AI accelerators, and board‑level power delivery into a cohesive high‑performance platform.

An overview of this role

As a Staff Engineer on GitLab's Software Composition Analysis team, you'll drive hands-on implementation of security features that help customers understand and manage risks in their software supply chain. Your focus will be on enhancing GitLab's SCA capabilities in dependency scanning and container scanning. You'll work directly on architecture and technical implementation and help the team push forward on three core goals: Gather (introducing data points that help customers understand the urgency of issues, like reachability analysis and supply chain poisoning detection), Integrate (providing other teams with innovative collection techniques for better workflows), and Optimize (solving data correlation at massive scale). You'll contribute hands-on code, help solve novel technical challenges, and establish patterns that improve how the distributed team works together across multiple time zones.

Examples of some future features that you may help build: 
- Dependency scanning for unmanaged C/C++ 
- Dependency Scanning for Yocto environments 
- Vulnerability detection using CPE-based matching against package metadata

What you’ll do

• Implement complex features in dependency scanning and container scanning, shipping improvements that increase scan coverage, improve accuracy, and drive adoption of GitLab's SCA capabilities
• Solve novel technical problems in SCA, establishing reusable patterns that reduce delivery time and improve engineering effectiveness across the team
• Guide architectural and implementation decisions in collaboration with engineering managers, product managers, and peer engineers to improve scalability, reliability, and delivery outcomes across the team's SCA architecture
• Contribute code, design reviews, and technical mentorship that raise quality standards, improve maintainability, and strengthen performance across the codebase
• Collaborate across GitLab's security domain to align SCA work with related efforts in vulnerability management and adjacent product areas, accelerating delivery of shared roadmap goals and improving coordination across related security efforts
• Identify and resolve technical debt, prioritizing changes that improve team velocity, code health, and long-term maintainability across the team's core SCA services
• Translate product needs and customer feedback into technical solutions in partnership with product, UX, and security stakeholders, delivering features that address high-impact customer risks and advance shared roadmap goals

What you’ll bring

• Hands-on experience in Software Composition Analysis and the ability to contribute to complex security features in dependency scanning and container scanning
• Deep hands-on expertise in building and evolving dependency scanning and container scanning analyzers
• Demonstrated ability to design solutions that balance complexity, performance, and maintainability
• Expertise with backend technologies, particularly Go and/or Ruby on Rails, with ability to pick up new technologies quickly
• Familiarity with cloud providers like GCP, CloudFlare, or AWS
• Ability to evaluate technical tradeoffs in SCA and security tooling, with proven success delivering maintainable solutions that help customers manage software supply chain risk
• Ability to work effectively in distributed, async-first teams across multiple time zones
• Experience explaining complex technical and security concepts to engineers and stakeholders

About the team

The Software Composition Analysis team is part of GitLab's Sec Engineering group, and we focus on building capabilities that help customers identify and manage risks in their software supply chain. We work across areas including dependency scanning, container scanning, and license scanning, and we work closely with product, UX, security, and adjacent engineering teams to close important feature gaps in GitLab's platform. Our team members are distributed across regions including Europe and North America, so we rely on clear documentation, asynchronous communication, and thoughtful coordination across time zones. This opportunity is centered on helping us deliver complex security features while balancing hands-on technical progress with strong team execution.